Issued Patents 2004
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6821864 | Method to achieve increased trench depth, independent of CD as defined by lithography | Subhash B. Kulkarni, Gangadhara S. Mathad, Rajiv Ranade | 2004-11-23 |
| 6809005 | Method to fill deep trench structures with void-free polysilicon or silicon | Rajiv Ranade, Gangadhara S. Mathad, Subhash B. Kulkarni | 2004-10-26 |
| 6797604 | Method for manufacturing device substrate with metal back-gate and structure formed thereby | Lijuan Huang, Fenton R. McFeely, Paul M. Solomon, Hon-Sum Philip Wong | 2004-09-28 |
| 6762101 | Damascene double-gate FET | Erin C. Jones, Paul M. Solomon, Hon-Sum Philip Wong | 2004-07-13 |
| 6759710 | Self-aligned double-gate MOSFET by selective epitaxy and silicon wafer bonding techniques | Guy M. Cohen, Yuan Taur, Hon-Sum Philip Wong | 2004-07-06 |
| 6724449 | Vertical aligned liquid crystal display and method using dry deposited alignment layer films | Paul S. Andry, Chen Cai, Praveen Chaudhari, James P. Doyle, Eileen A. Galligan +3 more | 2004-04-20 |
| 6716708 | Self-aligned silicide process utilizing ion implants for reduced silicon consumption and control of the silicide formation temperature and structure formed thereby | Cyril Cabral, Jr., Guy M. Cohen, Kathryn Guarini, Christian Lavoie, Ronnen Andrew Roy +1 more | 2004-04-06 |
| 6692256 | Interactive tutorial | Wassim Melhem, Dirk Alexander Seelemann, II, Vito Spatafora, Michael Starkey | 2004-02-17 |
| 6690072 | Method and structure for ultra-low contact resistance CMOS formed by vertically self-aligned CoSi2 on raised source drain Si/SiGe device | Cyril Cabral, Jr., Roy A. Carruthers, Jack O. Chu, Guy M. Cohen, Steven J. Koester +2 more | 2004-02-10 |