Issued Patents 2004
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6835633 | SOI wafers with 30-100 å buried oxide (BOX) created by wafer bonding using 30-100 å thin oxide as bonding layer | Diane C. Boyd, Hussein I. Hanafi, Dominic J. Schepis, Leathen Shi | 2004-12-28 |
| 6833569 | Self-aligned planar double-gate process by amorphization | Omer H. Dokumaci, Bruce B. Doris, Suryanarayan G. Hegde, Meikei Ieong | 2004-12-21 |
| 6797553 | Method for making multiple threshold voltage FET using multiple work-function gate materials | James W. Adkisson, Arne Ballantine, Ramachandra Divakaruni, Jeffrey B. Johnson, Hon-Sum Philip Wong | 2004-09-28 |
| 6762101 | Damascene double-gate FET | Kevin K. Chan, Paul M. Solomon, Hon-Sum Philip Wong | 2004-07-13 |
| 6686630 | Damascene double-gate MOSFET structure and its fabrication method | Hussein I. Hanafi, Cheruvu Murthy, Philip J. Oldiges, Leathen Shi | 2004-02-03 |