Issued Patents 2004
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6833569 | Self-aligned planar double-gate process by amorphization | Omer H. Dokumaci, Suryanarayan G. Hegde, Meikei Ieong, Erin C. Jones | 2004-12-21 |
| 6825529 | Stress inducing spacers | Dureseti Chidambarrao, Omer H. Dokumaci, Jack A. Mandelman, Xavier Baie | 2004-11-30 |
| 6812105 | Ultra-thin channel device with raised source and drain and solid source extension doping | Omer H. Dokumaci | 2004-11-02 |
| 6806534 | Damascene method for improved MOS transistor | Omer H. Dokumaci, Oleg Gluschenkov, Jack A. Mandelman, Carl Radens | 2004-10-19 |
| 6803315 | Method for blocking implants from the gate of an electronic device via planarizing films | Omer H. Dokumaci | 2004-10-12 |
| 6790733 | Preserving TEOS hard mask using COR for raised source-drain including removable/disposable spacer | Wesley C. Natzle, Sadanand V. Deshpande, Renee T. Mo, Patricia A. O'Neil | 2004-09-14 |
| 6780694 | MOS transistor | Omer H. Dokumaci, Jack A. Mandelman, Carl Radens | 2004-08-24 |
| 6764883 | Amorphous and polycrystalline silicon nanolaminate | Omer H. Dokumaci, Oleg Gluschenkov, Michael Belyanksy | 2004-07-20 |
| 6717216 | SOI based field effect transistor having a compressive film in undercut area under the channel and a method of making the device | Dureseti Chidambarrao, Xavier Baie, Jack A. Mandelman, Devendra K. Sadana, Dominic J. Schepis | 2004-04-06 |
| 6709926 | High performance logic and high density embedded dram with borderless contact and antispacer | Dureseti Chidambarrao, Omer H. Dokumaci, Oleg Gluschenkov, Rajarao Jammy, Jack A. Mandelman | 2004-03-23 |
| 6686637 | Gate structure with independently tailored vertical doping profile | Omer H. Dokumaci, Oleg Gluschenkov, Jack A. Mandelman, Carl Radens | 2004-02-03 |