Issued Patents 2004
Showing 1–25 of 32 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6833305 | Vertical DRAM punchthrough stop self-aligned to storage trench | Dureseti Chidambarrao, Ramachandra Divakaruni | 2004-12-21 |
| 6831006 | Structure and method for eliminating metal contact to P-well or N-well shorts or high leakage paths using polysilicon liner | Ramachandra Divakaruni, Haining Yang | 2004-12-14 |
| 6818528 | Method for multi-depth trench isolation | Ramachandra Divakaruni | 2004-11-16 |
| 6818487 | Self-aligned, planarized thin-film transistors, devices employing the same, and methods of fabrication thereof | Louis L. Hsu, William R. Tonti, Li-Kong Wang | 2004-11-16 |
| 6815749 | Backside buried strap for SOI DRAM trench capacitor | Herbert L. Ho | 2004-11-09 |
| 6808981 | Method for fabricating 6F2 trench DRAM cell with double-gated vertical MOSFET and self-aligned STI | Ramachandra Divakaruni, Carl Radens, Gary B. Bronner | 2004-10-26 |
| 6809372 | Flash memory structure using sidewall floating gate | Jeffrey P. Gambino, Louis L. Hsu, Donald C. Wheeler | 2004-10-26 |
| 6809368 | TTO nitride liner for improved collar protection and TTO reliability | Rama Divakaruni, Thomas W. Dyer, Rajeev Malik, Venkatachalam C. Jaiprakash | 2004-10-26 |
| 6790722 | Logic SOI structure, process and application for vertical bipolar transistor | Ramachandra Divakaruni, Russell J. Houghton, Wilbur D. Pricer, William R. Tonti | 2004-09-14 |
| 6777737 | Vertical DRAM punchthrough stop self-aligned to storage trench | Dureseti Chidambarrao, Ramachandra Divakaruni | 2004-08-17 |
| 6777733 | Method for forming dual workfunction high-performance support MOSFETs in EDRAM arrays | Ramachandra Divakaruni, Carl Radens | 2004-08-17 |
| 6767789 | Method for interconnection between transfer devices and storage capacitors in memory cells and device formed thereby | Gary B. Bronner, David V. Horak, Toshiharu Furukawa | 2004-07-27 |
| 6762447 | Field-shield-trench isolation for gigabit DRAMs | Rama Divakaruni, Giuseppe Larosa, Ulrike Gruening, Carl Radens | 2004-07-13 |
| 6759291 | Self-aligned near surface strap for high density trench DRAMS | Ramachandra Divakaruni, Jochen Beintner, Ulrike Gruening, Johann Alsmeier, Gary B. Bronner | 2004-07-06 |
| 6759292 | Method for fabricating a trench capacitor | Mihel Seitz, Michael P. Chudzik | 2004-07-06 |
| 6759702 | Memory cell with vertical transistor and trench capacitor with reduced burried strap | Carl Radens, Ramachandra Divakaruni | 2004-07-06 |
| 6750097 | Method of fabricating a patterened SOI embedded DRAM/eDRAM having a vertical device cell and device formed thereby | Ramachandra Divakaruni | 2004-06-15 |
| 6740920 | Vertical MOSFET with horizontally graded channel doping | Dureseti Chidambarrao, Kil-Ho Lee, Kevin McStay, Rajesh Rengarajan | 2004-05-25 |
| 6734056 | Self-aligned punch through stop for 6F2 rotated hybrid DRAM cell | Dureseti Chidambarrao | 2004-05-11 |
| 6727141 | DRAM having offset vertical transistors and method | Gary B. Bronner, Ramachandra Divakaruni, Byeong Y. Kim | 2004-04-27 |
| 6727539 | Embedded vertical DRAM arrays with silicided bitline and polysilicon interconnect | Ramachandra Divakaruni, Ulrike Gruening, Larry Nesbit, Carl Radens | 2004-04-27 |
| 6724029 | Twin-cell flash memory structure and method | Louis L. Hsu, Chung H. Lam, Carl Radens, William R. Tonti | 2004-04-20 |
| 6724088 | Quantum conductive barrier for contact to shallow diffusion region | Rajarao Jammy | 2004-04-20 |
| 6724031 | Method for preventing strap-to-strap punch through in vertical DRAMs | Hiroyuki Akatsu, Dureseti Chidambarrao, Ramachandra Divakaruni, Carl Radens | 2004-04-20 |
| 6720602 | Dynamic random access memory (DRAM) cell with folded bitline vertical transistor and method of producing the same | Lawrence A. Clevenger, Louis L. Hsu, Carl Radens | 2004-04-13 |