Issued Patents 2004
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6833305 | Vertical DRAM punchthrough stop self-aligned to storage trench | Jack A. Mandelman, Dureseti Chidambarrao | 2004-12-21 |
| 6831006 | Structure and method for eliminating metal contact to P-well or N-well shorts or high leakage paths using polysilicon liner | Jack A. Mandelman, Haining Yang | 2004-12-14 |
| 6830968 | Simplified top oxide late process | Deok-kee Kim | 2004-12-14 |
| 6818528 | Method for multi-depth trench isolation | Jack A. Mandelman | 2004-11-16 |
| 6808981 | Method for fabricating 6F2 trench DRAM cell with double-gated vertical MOSFET and self-aligned STI | Jack A. Mandelman, Carl Radens, Gary B. Bronner | 2004-10-26 |
| 6797553 | Method for making multiple threshold voltage FET using multiple work-function gate materials | James W. Adkisson, Arne Ballantine, Jeffrey B. Johnson, Erin C. Jones, Hon-Sum Philip Wong | 2004-09-28 |
| 6790722 | Logic SOI structure, process and application for vertical bipolar transistor | Russell J. Houghton, Jack A. Mandelman, Wilbur D. Pricer, William R. Tonti | 2004-09-14 |
| 6787838 | Trench capacitor DRAM cell using buried oxide as array top oxide | Dureseti Chidambarrao, Deok-kee Kim | 2004-09-07 |
| 6777737 | Vertical DRAM punchthrough stop self-aligned to storage trench | Jack A. Mandelman, Dureseti Chidambarrao | 2004-08-17 |
| 6777733 | Method for forming dual workfunction high-performance support MOSFETs in EDRAM arrays | Jack A. Mandelman, Carl Radens | 2004-08-17 |
| 6767781 | Structure and method of forming bitline contacts for a vertical DRAM array using a line bitline contact mask | Larry Nesbit, Jonathan E. Faltermeier, Wolfgang Bergner | 2004-07-27 |
| 6759291 | Self-aligned near surface strap for high density trench DRAMS | Jochen Beintner, Jack A. Mandelman, Ulrike Gruening, Johann Alsmeier, Gary B. Bronner | 2004-07-06 |
| 6759702 | Memory cell with vertical transistor and trench capacitor with reduced burried strap | Carl Radens, Jack A. Mandelman | 2004-07-06 |
| 6750097 | Method of fabricating a patterened SOI embedded DRAM/eDRAM having a vertical device cell and device formed thereby | Jack A. Mandelman | 2004-06-15 |
| 6727540 | Structure and method of fabricating embedded DRAM having a vertical device array and a bordered bitline contact | Babar A. Khan, Carl Radens | 2004-04-27 |
| 6727539 | Embedded vertical DRAM arrays with silicided bitline and polysilicon interconnect | Ulrike Gruening, Jack A. Mandelman, Larry Nesbit, Carl Radens | 2004-04-27 |
| 6727141 | DRAM having offset vertical transistors and method | Gary B. Bronner, Byeong Y. Kim, Jack A. Mandelman | 2004-04-27 |
| 6724031 | Method for preventing strap-to-strap punch through in vertical DRAMs | Hiroyuki Akatsu, Dureseti Chidambarrao, Jack A. Mandelman, Carl Radens | 2004-04-20 |
| 6703274 | Buried strap with limited outdiffusion and vertical transistor DRAM | Dureseti Chidambarrao, Jack A. Mandelman, Raymond Van Roijen | 2004-03-09 |
| 6693041 | Self-aligned STI for narrow trenches | Jack A. Mandelman, Carl Radens | 2004-02-17 |
| 6686668 | Structure and method of forming bitline contacts for a vertical DRAM array using a line bitline contact mask | Larry Nesbit, Johnathan E. Faltermeier, Wolfgang Bergner | 2004-02-03 |
| 6686617 | Semiconductor chip having both compact memory and high performance logic | Paul D. Agnello, Bomy Chen, Scott W. Crowder, Subramanian S. Iyer, Dennis Sinitsky | 2004-02-03 |