DC

Dureseti Chidambarrao

IBM: 12 patents #35 of 5,464Top 1%
📍 Weston, CT: #1 of 12 inventorsTop 9%
🗺 Connecticut: #7 of 2,707 inventorsTop 1%
Overall (2004): #971 of 270,089Top 1%
12
Patents 2004

Issued Patents 2004

Showing 1–12 of 12 patents

Patent #TitleCo-InventorsDate
6833305 Vertical DRAM punchthrough stop self-aligned to storage trench Jack A. Mandelman, Ramachandra Divakaruni 2004-12-21
6825529 Stress inducing spacers Omer H. Dokumaci, Bruce B. Doris, Jack A. Mandelman, Xavier Baie 2004-11-30
6803270 CMOS performance enhancement using localized voids and extended defects Omer H. Dokumachi, Suryanarayan G. Hegde 2004-10-12
6787838 Trench capacitor DRAM cell using buried oxide as array top oxide Ramachandra Divakaruni, Deok-kee Kim 2004-09-07
6777737 Vertical DRAM punchthrough stop self-aligned to storage trench Jack A. Mandelman, Ramachandra Divakaruni 2004-08-17
6740920 Vertical MOSFET with horizontally graded channel doping Kil-Ho Lee, Jack A. Mandelman, Kevin McStay, Rajesh Rengarajan 2004-05-25
6734056 Self-aligned punch through stop for 6F2 rotated hybrid DRAM cell Jack A. Mandelman 2004-05-11
6724031 Method for preventing strap-to-strap punch through in vertical DRAMs Hiroyuki Akatsu, Ramachandra Divakaruni, Jack A. Mandelman, Carl Radens 2004-04-20
6717216 SOI based field effect transistor having a compressive film in undercut area under the channel and a method of making the device Bruce B. Doris, Xavier Baie, Jack A. Mandelman, Devendra K. Sadana, Dominic J. Schepis 2004-04-06
6709926 High performance logic and high density embedded dram with borderless contact and antispacer Omer H. Dokumaci, Bruce B. Doris, Oleg Gluschenkov, Rajarao Jammy, Jack A. Mandelman 2004-03-23
6707095 Structure and method for improved vertical MOSFET DRAM cell-to-cell isolation Jack A. Mandelman, Carl Radens 2004-03-16
6703274 Buried strap with limited outdiffusion and vertical transistor DRAM Ramachandra Divakaruni, Jack A. Mandelman, Raymond Van Roijen 2004-03-09