Issued Patents 2004
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6833569 | Self-aligned planar double-gate process by amorphization | Bruce B. Doris, Suryanarayan G. Hegde, Meikei Ieong, Erin C. Jones | 2004-12-21 |
| 6825529 | Stress inducing spacers | Dureseti Chidambarrao, Bruce B. Doris, Jack A. Mandelman, Xavier Baie | 2004-11-30 |
| 6812105 | Ultra-thin channel device with raised source and drain and solid source extension doping | Bruce B. Doris | 2004-11-02 |
| 6806534 | Damascene method for improved MOS transistor | Bruce B. Doris, Oleg Gluschenkov, Jack A. Mandelman, Carl Radens | 2004-10-19 |
| 6803315 | Method for blocking implants from the gate of an electronic device via planarizing films | Bruce B. Doris | 2004-10-12 |
| 6780694 | MOS transistor | Bruce B. Doris, Jack A. Mandelman, Carl Radens | 2004-08-24 |
| 6764883 | Amorphous and polycrystalline silicon nanolaminate | Oleg Gluschenkov, Michael Belyanksy, Bruce B. Doris | 2004-07-20 |
| 6709926 | High performance logic and high density embedded dram with borderless contact and antispacer | Dureseti Chidambarrao, Bruce B. Doris, Oleg Gluschenkov, Rajarao Jammy, Jack A. Mandelman | 2004-03-23 |
| 6686637 | Gate structure with independently tailored vertical doping profile | Bruce B. Doris, Oleg Gluschenkov, Jack A. Mandelman, Carl Radens | 2004-02-03 |
| 6677646 | Method and structure of a disposable reversed spacer process for high performance recessed channel CMOS | Meikei Ieong, Thomas S. Kanarsky, Victor Ku | 2004-01-13 |