Issued Patents 2003
Showing 26–50 of 58 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6601145 | Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers that uses dynamic hardware/software controls | James Stephen Fields, Jr., Sanjeev Ghai, Guy L. Guthrie, Jody B. Joyner | 2003-07-29 |
| 6601144 | Dynamic cache management in a symmetric multiprocessor system via snoop operation sequence analysis | John Steven Dodson, James Stephen Fields, Jr., Guy L. Guthrie | 2003-07-29 |
| 6598118 | Data processing system with HSA (hashed storage architecture) | Leo James Clark, John S. Dodson, Guy L. Guthrie, Jerry Don Lewis | 2003-07-22 |
| 6591321 | Multiprocessor system bus protocol with group addresses, responses, and priorities | James Stephen Fields, Jr., Guy L. Guthrie, Jody B. Joyner, Jerry Don Lewis | 2003-07-08 |
| 6591307 | Multi-node data processing system and method of queue management in which a queued operation is speculatively cancelled in response to a partial combined response | James Stephen Fields, Jr., Guy L. Guthrie, Jody B. Joyner, Jerry Don Lewis | 2003-07-08 |
| 6587926 | Incremental tag build for hierarchical memory architecture | John Steven Dodson, Jerry Don Lewis | 2003-07-01 |
| 6587925 | Elimination of vertical bus queueing within a hierarchical memory architecture | John Steven Dodson, Jerry Don Lewis | 2003-07-01 |
| 6587924 | Scarfing within a hierarchical memory architecture | John Steven Dodson, Jerry Don Lewis | 2003-07-01 |
| 6581115 | Data processing system with configurable memory bus and scalability ports | Lakshminarayana B. Arimilli, Leo James Clark, James S. Fields, Jr. | 2003-06-17 |
| 6581139 | Set-associative cache memory having asymmetric latency among sets | Lakshminarayana B. Arimilli, John Steven Dodson, James Stephen Fields, Jr., Guy L. Guthrie | 2003-06-17 |
| 6581116 | Method and apparatus for high performance transmission of ordered packets on a bus within a data processing system | Vicente Enrique Chung, Warren E. Maule | 2003-06-17 |
| 6574714 | Efficient instruction cache coherency maintenance mechanism for scalable multiprocessor computer system with write-back data cache | John Steven Dodson, Guy L. Guthrie | 2003-06-03 |
| 6574719 | Method and apparatus for concurrently communicating with multiple embedded dynamic random access memory devices | James Stephen Fields, Jr., Sanjeev Ghai, Praveen S. Reddy, William J. Starke | 2003-06-03 |
| 6571322 | Multiprocessor computer system with sectored cache line mechanism for cache intervention | John Steven Dodson, Guy L. Guthrie | 2003-05-27 |
| 6553442 | Bus master for SMP execution of global operations utilizing a single token with implied release | John Steven Dodson, Jody B. Joyner, Jerry Don Lewis | 2003-04-22 |
| 6553463 | Method and system for high speed access to a banked cache memory | Lakshminarayana B. Arimilli, James Stephen Fields, Jr., Sanjeev Ghai, Praveen S. Reddy | 2003-04-22 |
| 6553462 | Multiprocessor computer system with sectored cache line mechanism for load and store operations | John Steven Dodson, Guy L. Guthrie | 2003-04-22 |
| 6553447 | Data processing system with fully interconnected system architecture (FISA) | Leo James Clark, Jerry Don Lewis, Bradley McCredie | 2003-04-22 |
| 6549989 | Extended cache coherency protocol with a “lock released” state | Lakshminarayana B. Arimilli, John Steven Dodson, Guy L. Guthrie, William J. Starke | 2003-04-15 |
| 6546469 | Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers | James Stephen Fields, Jr., Sanjeev Ghai, Guy L. Guthrie, Jody B. Joyner | 2003-04-08 |
| 6546470 | Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers with banked directory implementation | James Stephen Fields, Jr., Sanjeev Ghai, Guy L. Guthrie, Jody B. Joyner | 2003-04-08 |
| 6546468 | Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers performing directory update | James Stephen Fields, Jr., Sanjeev Ghai, Guy L. Guthrie, Jody B. Joyner | 2003-04-08 |
| 6535957 | System bus read data transfers with bus utilization based data ordering | Vicente Enrique Chung, Guy L. Guthrie, Jody B. Joyner | 2003-03-18 |
| 6535939 | Dynamically configurable memory bus and scalability ports via hardware monitored bus utilizations | Lakshminarayana B. Arimilli, Leo James Clark, James S. Fields, Jr. | 2003-03-18 |
| 6532521 | Mechanism for high performance transfer of speculative request data between levels of cache hierarchy | Lakshminarayana B. Arimilli, Leo James Clark, John Steven Dodson, Guy L. Guthrie, James Stephen Fields, Jr. | 2003-03-11 |