Issued Patents 2003
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6658556 | Hashing a target address for a memory access instruction in order to determine prior to execution which particular load/store unit processes the instruction | Ravi Kumar Arimilli, John S. Dodson, Guy L. Guthrie, Jerry Don Lewis | 2003-12-02 |
| 6606666 | Method and system for controlling information flow between a producer and a buffer in a high frequency digital system | Robert H. Bell, Jr., Robert Alan Cargnoni, William J. Starke | 2003-08-12 |
| 6604145 | Method and system for controlling information flow in a high frequency digital system from a producer to a buffering consumer via an intermediate buffer and a shared data path | Robert H. Bell, Jr., Robert Alan Cargnoni, William J. Starke | 2003-08-05 |
| 6601105 | Method and system for controlling information flow between a producer and multiple buffers in a high frequency digital system | Robert H. Bell, Jr., Robert Alan Cargnoni, William J. Starke | 2003-07-29 |
| 6598086 | Method and system for controlling information flow in a high frequency digital system from a producer to a buffering consumer via an intermediate buffer | Robert H. Bell, Jr., Robert Alan Cargnoni, William J. Starke | 2003-07-22 |
| 6598118 | Data processing system with HSA (hashed storage architecture) | Ravi Kumar Arimilli, John S. Dodson, Guy L. Guthrie, Jerry Don Lewis | 2003-07-22 |
| 6581115 | Data processing system with configurable memory bus and scalability ports | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, James S. Fields, Jr. | 2003-06-17 |
| 6553447 | Data processing system with fully interconnected system architecture (FISA) | Ravi Kumar Arimilli, Jerry Don Lewis, Bradley McCredie | 2003-04-22 |
| 6535939 | Dynamically configurable memory bus and scalability ports via hardware monitored bus utilizations | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, James S. Fields, Jr. | 2003-03-18 |
| 6532521 | Mechanism for high performance transfer of speculative request data between levels of cache hierarchy | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, John Steven Dodson, Guy L. Guthrie, James Stephen Fields, Jr. | 2003-03-11 |
| 6516404 | Data processing system having hashed architected processor facilities | Ravi Kumar Arimilli, John S. Dodson, Guy L. Guthrie, Jerry Don Lewis | 2003-02-04 |
| 6510494 | Time based mechanism for cached speculative data deallocation | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, John Steven Dodson, Guy L. Guthrie, James Stephen Fields, Jr. | 2003-01-21 |