Issued Patents 2003
Showing 1–25 of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6671712 | Multi-node data processing system having a non-hierarchical interconnect architecture | Ravi Kumar Arimilli, James Stephen Fields, Jr., Jody B. Joyner, Jerry Don Lewis | 2003-12-30 |
| 6662275 | Efficient instruction cache coherency maintenance mechanism for scalable multiprocessor computer system with store-through data cache | Ravi Kumar Arimilli, John Steven Dodson | 2003-12-09 |
| 6658556 | Hashing a target address for a memory access instruction in order to determine prior to execution which particular load/store unit processes the instruction | Ravi Kumar Arimilli, Leo James Clark, John S. Dodson, Jerry Don Lewis | 2003-12-02 |
| 6658539 | Super-coherent data mechanisms for shared caches in a multiprocessing system | Ravi Kumar Arimilli, William J. Starke, Derek E. Williams | 2003-12-02 |
| 6631450 | Symmetric multiprocessor address bus protocol with intra-cache line access information | Ravi Kumar Arimilli, John Steven Dodson, James Stephen Fields, Jr. | 2003-10-07 |
| 6629210 | Intelligent cache management mechanism via processor access sequence analysis | Ravi Kumar Arimilli, John Steven Dodson, James Stephen Fields, Jr. | 2003-09-30 |
| 6629214 | Extended cache coherency protocol with a persistent “lock acquired” state | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, John Steven Dodson, William J. Starke | 2003-09-30 |
| 6629212 | High speed lock acquisition mechanism with time parameterized cache coherency states | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, John Steven Dodson, William J. Starke | 2003-09-30 |
| 6629209 | Cache coherency protocol permitting sharing of a locked data granule | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, John Steven Dodson, William J. Starke | 2003-09-30 |
| 6625701 | Extended cache coherency protocol with a modified store instruction lock release indicator | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, John Steven Dodson, William J. Starke | 2003-09-23 |
| 6625660 | Multiprocessor speculation mechanism for efficiently managing multiple barrier operations | Ravi Kumar Arimilli, John Steven Dodson, Derek E. Williams | 2003-09-23 |
| 6615321 | Mechanism for collapsing store misses in an SMP computer system | Ravi Kumar Arimilli, John Steven Dodson | 2003-09-02 |
| 6615320 | Store collapsing mechanism for SMP computer system | Ravi Kumar Arimilli, John Steven Dodson | 2003-09-02 |
| 6609192 | System and method for asynchronously overlapping storage barrier operations with old and new storage operations | Ravi Kumar Arimilli, John Steven Dodson, Derek E. Williams | 2003-08-19 |
| 6606702 | Multiprocessor speculation mechanism with imprecise recycling of storage operations | Ravi Kumar Arimilli, John Steven Dodson, Derek E. Williams | 2003-08-12 |
| 6601144 | Dynamic cache management in a symmetric multiprocessor system via snoop operation sequence analysis | Ravi Kumar Arimilli, John Steven Dodson, James Stephen Fields, Jr. | 2003-07-29 |
| 6601145 | Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers that uses dynamic hardware/software controls | Ravi Kumar Arimilli, James Stephen Fields, Jr., Sanjeev Ghai, Jody B. Joyner | 2003-07-29 |
| 6598118 | Data processing system with HSA (hashed storage architecture) | Ravi Kumar Arimilli, Leo James Clark, John S. Dodson, Jerry Don Lewis | 2003-07-22 |
| 6591321 | Multiprocessor system bus protocol with group addresses, responses, and priorities | Ravi Kumar Arimilli, James Stephen Fields, Jr., Jody B. Joyner, Jerry Don Lewis | 2003-07-08 |
| 6591307 | Multi-node data processing system and method of queue management in which a queued operation is speculatively cancelled in response to a partial combined response | Ravi Kumar Arimilli, James Stephen Fields, Jr., Jody B. Joyner, Jerry Don Lewis | 2003-07-08 |
| 6581139 | Set-associative cache memory having asymmetric latency among sets | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, John Steven Dodson, James Stephen Fields, Jr. | 2003-06-17 |
| 6574714 | Efficient instruction cache coherency maintenance mechanism for scalable multiprocessor computer system with write-back data cache | Ravi Kumar Arimilli, John Steven Dodson | 2003-06-03 |
| 6571322 | Multiprocessor computer system with sectored cache line mechanism for cache intervention | Ravi Kumar Arimilli, John Steven Dodson | 2003-05-27 |
| 6553462 | Multiprocessor computer system with sectored cache line mechanism for load and store operations | Ravi Kumar Arimilli, John Steven Dodson | 2003-04-22 |
| 6549989 | Extended cache coherency protocol with a “lock released” state | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, John Steven Dodson, William J. Starke | 2003-04-15 |