Issued Patents 2003
Showing 1–25 of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6662216 | Fixed bus tags for SMP buses | Ravi Kumar Arimilli, Jerry Don Lewis | 2003-12-09 |
| 6662275 | Efficient instruction cache coherency maintenance mechanism for scalable multiprocessor computer system with store-through data cache | Ravi Kumar Arimilli, Guy L. Guthrie | 2003-12-09 |
| 6658538 | Non-uniform memory access (NUMA) data processing system having a page table including node-specific data storage and coherency control | Ravi Kumar Arimilli, James Stephen Fields, Jr. | 2003-12-02 |
| 6658536 | Cache-coherency protocol with recently read state for extending cache horizontally | Ravi Kumar Arimilli, John Michael Kaiser, Jerry Don Lewis | 2003-12-02 |
| 6654857 | Non-uniform memory access (NUMA) computer system having distributed global coherency management | Ravi Kumar Arimilli, James Stephen Fields, Jr. | 2003-11-25 |
| 6633959 | Non-uniform memory access (NUMA) data processing system that provides notification of remote deallocation of shared data | Ravi Kumar Arimilli, James Stephen Fields, Jr. | 2003-10-14 |
| 6631450 | Symmetric multiprocessor address bus protocol with intra-cache line access information | Ravi Kumar Arimilli, James Stephen Fields, Jr., Guy L. Guthrie | 2003-10-07 |
| 6629210 | Intelligent cache management mechanism via processor access sequence analysis | Ravi Kumar Arimilli, James Stephen Fields, Jr., Guy L. Guthrie | 2003-09-30 |
| 6629214 | Extended cache coherency protocol with a persistent “lock acquired” state | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Guy L. Guthrie, William J. Starke | 2003-09-30 |
| 6629212 | High speed lock acquisition mechanism with time parameterized cache coherency states | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Guy L. Guthrie, William J. Starke | 2003-09-30 |
| 6629209 | Cache coherency protocol permitting sharing of a locked data granule | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Guy L. Guthrie, William J. Starke | 2003-09-30 |
| 6625701 | Extended cache coherency protocol with a modified store instruction lock release indicator | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Guy L. Guthrie, William J. Starke | 2003-09-23 |
| 6625660 | Multiprocessor speculation mechanism for efficiently managing multiple barrier operations | Guy L. Guthrie, Ravi Kumar Arimilli, Derek E. Williams | 2003-09-23 |
| 6615321 | Mechanism for collapsing store misses in an SMP computer system | Ravi Kumar Arimilli, Guy L. Guthrie | 2003-09-02 |
| 6615322 | Two-stage request protocol for accessing remote memory data in a NUMA data processing system | Ravi Kumar Arimilli, James Stephen Fields, Jr. | 2003-09-02 |
| 6615320 | Store collapsing mechanism for SMP computer system | Ravi Kumar Arimilli, Guy L. Guthrie | 2003-09-02 |
| 6609192 | System and method for asynchronously overlapping storage barrier operations with old and new storage operations | Guy L. Guthrie, Ravi Kumar Arimilli, Derek E. Williams | 2003-08-19 |
| 6606702 | Multiprocessor speculation mechanism with imprecise recycling of storage operations | Guy L. Guthrie, Ravi Kumar Arimilli, Derek E. Williams | 2003-08-12 |
| 6601144 | Dynamic cache management in a symmetric multiprocessor system via snoop operation sequence analysis | Ravi Kumar Arimilli, James Stephen Fields, Jr., Guy L. Guthrie | 2003-07-29 |
| 6587926 | Incremental tag build for hierarchical memory architecture | Ravi Kumar Arimilli, Jerry Don Lewis | 2003-07-01 |
| 6587925 | Elimination of vertical bus queueing within a hierarchical memory architecture | Ravi Kumar Arimilli, Jerry Don Lewis | 2003-07-01 |
| 6587924 | Scarfing within a hierarchical memory architecture | Ravi Kumar Arimilli, Jerry Don Lewis | 2003-07-01 |
| 6581139 | Set-associative cache memory having asymmetric latency among sets | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, James Stephen Fields, Jr., Guy L. Guthrie | 2003-06-17 |
| 6574714 | Efficient instruction cache coherency maintenance mechanism for scalable multiprocessor computer system with write-back data cache | Ravi Kumar Arimilli, Guy L. Guthrie | 2003-06-03 |
| 6571322 | Multiprocessor computer system with sectored cache line mechanism for cache intervention | Ravi Kumar Arimilli, Guy L. Guthrie | 2003-05-27 |