Issued Patents 2003
Showing 26–33 of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6553462 | Multiprocessor computer system with sectored cache line mechanism for load and store operations | Ravi Kumar Arimilli, Guy L. Guthrie | 2003-04-22 |
| 6553442 | Bus master for SMP execution of global operations utilizing a single token with implied release | Ravi Kumar Arimilli, Jody B. Joyner, Jerry Don Lewis | 2003-04-22 |
| 6549989 | Extended cache coherency protocol with a “lock released” state | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Guy L. Guthrie, William J. Starke | 2003-04-15 |
| 6532521 | Mechanism for high performance transfer of speculative request data between levels of cache hierarchy | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Leo James Clark, Guy L. Guthrie, James Stephen Fields, Jr. | 2003-03-11 |
| 6516368 | Bus master and bus snooper for execution of global operations utilizing a single token for multiple operations with explicit release | Ravi Kumar Arimilli, Jody B. Joyner, Jerry Don Lewis | 2003-02-04 |
| 6510494 | Time based mechanism for cached speculative data deallocation | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Leo James Clark, Guy L. Guthrie, James Stephen Fields, Jr. | 2003-01-21 |
| 6507880 | Bus protocol, bus master and bus snooper for execution of global operations utilizing multiple tokens | Ravi Kumar Arimilli, Jody B. Joyner, Jerry Don Lewis | 2003-01-14 |
| 6505277 | Method for just-in-time delivery of load data by intervening caches | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Jerry Don Lewis | 2003-01-07 |