Issued Patents 2003
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6671712 | Multi-node data processing system having a non-hierarchical interconnect architecture | Ravi Kumar Arimilli, James Stephen Fields, Jr., Guy L. Guthrie, Jody B. Joyner | 2003-12-30 |
| 6662216 | Fixed bus tags for SMP buses | Ravi Kumar Arimilli, John Steven Dodson | 2003-12-09 |
| 6658556 | Hashing a target address for a memory access instruction in order to determine prior to execution which particular load/store unit processes the instruction | Ravi Kumar Arimilli, Leo James Clark, John S. Dodson, Guy L. Guthrie | 2003-12-02 |
| 6658536 | Cache-coherency protocol with recently read state for extending cache horizontally | Ravi Kumar Arimilli, John Steven Dodson, John Michael Kaiser | 2003-12-02 |
| 6598118 | Data processing system with HSA (hashed storage architecture) | Ravi Kumar Arimilli, Leo James Clark, John S. Dodson, Guy L. Guthrie | 2003-07-22 |
| 6591321 | Multiprocessor system bus protocol with group addresses, responses, and priorities | Ravi Kumar Arimilli, James Stephen Fields, Jr., Guy L. Guthrie, Jody B. Joyner | 2003-07-08 |
| 6591307 | Multi-node data processing system and method of queue management in which a queued operation is speculatively cancelled in response to a partial combined response | Ravi Kumar Arimilli, James Stephen Fields, Jr., Guy L. Guthrie, Jody B. Joyner | 2003-07-08 |
| 6587925 | Elimination of vertical bus queueing within a hierarchical memory architecture | Ravi Kumar Arimilli, John Steven Dodson | 2003-07-01 |
| 6587924 | Scarfing within a hierarchical memory architecture | Ravi Kumar Arimilli, John Steven Dodson | 2003-07-01 |
| 6587926 | Incremental tag build for hierarchical memory architecture | Ravi Kumar Arimilli, John Steven Dodson | 2003-07-01 |
| 6553447 | Data processing system with fully interconnected system architecture (FISA) | Ravi Kumar Arimilli, Leo James Clark, Bradley McCredie | 2003-04-22 |
| 6553442 | Bus master for SMP execution of global operations utilizing a single token with implied release | Ravi Kumar Arimilli, John Steven Dodson, Jody B. Joyner | 2003-04-22 |
| 6519665 | Multi-node data processing system and communication protocol in which a stomp signal is propagated to cancel a prior request | Ravi Kumar Arimilli, James Stephen Fields, Jr., Guy L. Guthrie, Jody B. Joyner | 2003-02-11 |
| 6519649 | Multi-node data processing system and communication protocol having a partial combined response | Ravi Kumar Arimilli, James Stephen Fields, Jr., Guy L. Guthrie, Jody B. Joyner | 2003-02-11 |
| 6516368 | Bus master and bus snooper for execution of global operations utilizing a single token for multiple operations with explicit release | Ravi Kumar Arimilli, John Steven Dodson, Jody B. Joyner | 2003-02-04 |
| 6516404 | Data processing system having hashed architected processor facilities | Ravi Kumar Arimilli, Leo James Clark, John S. Dodson, Guy L. Guthrie | 2003-02-04 |
| 6507880 | Bus protocol, bus master and bus snooper for execution of global operations utilizing multiple tokens | Ravi Kumar Arimilli, John Steven Dodson, Jody B. Joyner | 2003-01-14 |
| 6505277 | Method for just-in-time delivery of load data by intervening caches | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, John Steven Dodson | 2003-01-07 |