Issued Patents 2003
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6671712 | Multi-node data processing system having a non-hierarchical interconnect architecture | Ravi Kumar Arimilli, Guy L. Guthrie, Jody B. Joyner, Jerry Don Lewis | 2003-12-30 |
| 6658538 | Non-uniform memory access (NUMA) data processing system having a page table including node-specific data storage and coherency control | Ravi Kumar Arimilli, John Steven Dodson | 2003-12-02 |
| 6654857 | Non-uniform memory access (NUMA) computer system having distributed global coherency management | Ravi Kumar Arimilli, John Steven Dodson | 2003-11-25 |
| 6633959 | Non-uniform memory access (NUMA) data processing system that provides notification of remote deallocation of shared data | Ravi Kumar Arimilli, John Steven Dodson | 2003-10-14 |
| 6631450 | Symmetric multiprocessor address bus protocol with intra-cache line access information | Ravi Kumar Arimilli, John Steven Dodson, Guy L. Guthrie | 2003-10-07 |
| 6629210 | Intelligent cache management mechanism via processor access sequence analysis | Ravi Kumar Arimilli, John Steven Dodson, Guy L. Guthrie | 2003-09-30 |
| 6622222 | Sequencing data on a shared data bus via a memory buffer to prevent data overlap during multiple memory read operations | Ravi Kumar Arimilli, Warren E. Maule | 2003-09-16 |
| 6615322 | Two-stage request protocol for accessing remote memory data in a NUMA data processing system | Ravi Kumar Arimilli, John Steven Dodson | 2003-09-02 |
| 6606680 | Method and apparatus for accessing banked embedded dynamic random access memory devices | Ravi Kumar Arimilli, Sanjeev Ghai, Praveen S. Reddy, William J. Starke | 2003-08-12 |
| 6601145 | Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers that uses dynamic hardware/software controls | Ravi Kumar Arimilli, Sanjeev Ghai, Guy L. Guthrie, Jody B. Joyner | 2003-07-29 |
| 6601144 | Dynamic cache management in a symmetric multiprocessor system via snoop operation sequence analysis | Ravi Kumar Arimilli, John Steven Dodson, Guy L. Guthrie | 2003-07-29 |
| 6591307 | Multi-node data processing system and method of queue management in which a queued operation is speculatively cancelled in response to a partial combined response | Ravi Kumar Arimilli, Guy L. Guthrie, Jody B. Joyner, Jerry Don Lewis | 2003-07-08 |
| 6591321 | Multiprocessor system bus protocol with group addresses, responses, and priorities | Ravi Kumar Arimilli, Guy L. Guthrie, Jody B. Joyner, Jerry Don Lewis | 2003-07-08 |
| 6581139 | Set-associative cache memory having asymmetric latency among sets | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, John Steven Dodson, Guy L. Guthrie | 2003-06-17 |
| 6574719 | Method and apparatus for concurrently communicating with multiple embedded dynamic random access memory devices | Ravi Kumar Arimilli, Sanjeev Ghai, Praveen S. Reddy, William J. Starke | 2003-06-03 |
| 6553463 | Method and system for high speed access to a banked cache memory | Lakshminarayana B. Arimilli, Ravi Kumar Arimilli, Sanjeev Ghai, Praveen S. Reddy | 2003-04-22 |
| 6546470 | Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers with banked directory implementation | Ravi Kumar Arimilli, Sanjeev Ghai, Guy L. Guthrie, Jody B. Joyner | 2003-04-08 |
| 6546469 | Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers | Ravi Kumar Arimilli, Sanjeev Ghai, Guy L. Guthrie, Jody B. Joyner | 2003-04-08 |
| 6546468 | Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers performing directory update | Ravi Kumar Arimilli, Sanjeev Ghai, Guy L. Guthrie, Jody B. Joyner | 2003-04-08 |
| 6539487 | System for dynamically selecting maximum number of accessible banks of memory per cycle by monitoring actual power to each of the banks to determine the number of accessible banks | Sanjeev Ghai, Praveen S. Reddy | 2003-03-25 |
| 6532521 | Mechanism for high performance transfer of speculative request data between levels of cache hierarchy | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Leo James Clark, John Steven Dodson, Guy L. Guthrie | 2003-03-11 |
| 6532519 | Apparatus for associating cache memories with processors within a multiprocessor data processing system | Ravi Kumar Arimilli, Sanjeev Ghai, Jody B. Joyner | 2003-03-11 |
| 6519649 | Multi-node data processing system and communication protocol having a partial combined response | Ravi Kumar Arimilli, Guy L. Guthrie, Jody B. Joyner, Jerry Don Lewis | 2003-02-11 |
| 6519665 | Multi-node data processing system and communication protocol in which a stomp signal is propagated to cancel a prior request | Ravi Kumar Arimilli, Guy L. Guthrie, Jody B. Joyner, Jerry Don Lewis | 2003-02-11 |
| 6510494 | Time based mechanism for cached speculative data deallocation | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Leo James Clark, John Steven Dodson, Guy L. Guthrie | 2003-01-21 |