Issued Patents 2003
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6664150 | Active well schemes for SOI technology | William F. Clark, Jr., Edward J. Nowak, Minh H. Tong | 2003-12-16 |
| 6660596 | Double planar gated SOI MOSFET structure | James W. Adkisson, John A. Bracchitta, John J. Ellis-Monaghan, Jerome B. Lasky, Effendi Leobandung +1 more | 2003-12-09 |
| 6646305 | Grounded body SOI SRAM cell | Fariborz Assaderaghi, Andres Bryant, Peter E. Cottrell, Robert J. Gauthier, Jr., Randy W. Mann +1 more | 2003-11-11 |
| 6624478 | High mobility transistors in SOI and method for forming | Brent A. Anderson, Xavier Baie, Randy W. Mann, Edward J. Nowak | 2003-09-23 |
| 6624031 | Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure | Wagdi W. Abadeer, Eric Adler, Jeffrey S. Brown, Robert J. Gauthier, Jr., Jonathan M. McKenna +2 more | 2003-09-23 |
| 6610607 | Method to define and tailor process limited lithographic features using a modified hard mask process | Douglas S. Armbrust, Dale W. Martin, Sylvia Tousley | 2003-08-26 |
| 6583469 | Self-aligned dog-bone structure for FinFET applications and methods to fabricate the same | David M. Fried, Timothy J. Hoague, Edward J. Nowak | 2003-06-24 |
| 6573541 | Charge coupled device with channel well | William A. Klaasen, Gary Dale Pittman | 2003-06-03 |
| 6563131 | Method and structure of a dual/wrap-around gate field effect transistor | James W. Adkisson, Paul D. Agnello, Arne Ballantine, Christopher S. Putnam | 2003-05-13 |
| 6557163 | Method of photolithographic critical dimension control by using reticle measurements in a control algorithm | Craig E. Schneider, John S. Smyth, Andrew J. Watts | 2003-04-29 |
| 6545333 | Light controlled silicon on insulator device | Mark B. Ketchen, Edward J. Nowak, Keith C. Stevens | 2003-04-08 |
| 6534389 | Dual level contacts and method for forming | Thomas G. Ference, Kurt R. Kimmel, Alain Loiseau | 2003-03-18 |
| 6525371 | Self-aligned non-volatile random access memory cell and process to make the same | Jeffrey B. Johnson, Chung H. Lam, Dana Lee, Dale W. Martin | 2003-02-25 |
| 6504207 | Method to create EEPROM memory structures integrated with high performance logic and NVRAM, and operating conditions for the same | Bomy Chen, Jay G. Harrington, Kevin M. Houlihan, Dennis Hoyniak, Chung H. Lam +2 more | 2003-01-07 |