Issued Patents 2002
Showing 26–33 of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6380027 | Dual tox trench dram structures and process using V-groove | Toshiharu Furukawa, Jeffrey P. Gambino, Edward W. Kiewra, Jack A. Mandelman, William R. Tonti +1 more | 2002-04-30 |
| 6376324 | Collar process for reduced deep trench edge bias | Jack A. Mandelman, Ramachandra Divakaruni, Ulrike Gruening, Akira Sudo | 2002-04-23 |
| 6355531 | Method for fabricating semiconductor devices with different properties using maskless process | Jack A. Mandelman, Louis L. Hsu, William R. Tonti, Li-Kong Wang | 2002-03-12 |
| 6352892 | Method of making DRAM trench capacitor | Rajarao Jammy, Jack A. Mandelman | 2002-03-05 |
| 6348374 | Process for 4F2 STC cell having vertical MOSFET and buried-bitline conductor structure | Satish D. Athavale, Gary B. Bronner, Ramachandra Divakaruni, Ulrike Gruening, Jack A. Mandelman | 2002-02-19 |
| 6344389 | Self-aligned damascene interconnect | Gary B. Bronner, Jeffrey P. Gambino | 2002-02-05 |
| 6339241 | Structure and process for 6F2 trench capacitor DRAM cell with vertical MOSFET and 3F bitline pitch | Jack A. Mandelman, Ramachandra Divakaruni, Ulrike Gruening | 2002-01-15 |
| 6339239 | DRAM cell layout for node capacitance enhancement | Johann Alsmeier | 2002-01-15 |