Issued Patents 2002
Showing 1–25 of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6501117 | Static self-refreshing DRAM structure and operating mode | Gary B. Bronner, Ramachandra Divakaruni, Jack A. Mandelman | 2002-12-31 |
| 6486526 | Crack stop between neighboring fuses for protection from fuse blow damage | Chandrasekhar Narayan, Edward W. Kiewra, Axel Brintzinger | 2002-11-26 |
| 6455886 | Structure and process for compact cell area in a stacked capacitor cell array | Jack A. Mandelman, Ramachandra Divakaruni | 2002-09-24 |
| 6451648 | Process for buried-strap self-aligned to deep storage trench | Ulrike Gruening, Jack A. Mandelman | 2002-09-17 |
| 6452224 | Method for manufacture of improved deep trench eDRAM capacitor and structure produced thereby | Jack A. Mandelman | 2002-09-17 |
| 6452110 | Patterning microelectronic features without using photoresists | Lawrence A. Clevenger, Louis L. Hsu, Li-Kong Wang, Keith Kwong Hon Wong | 2002-09-17 |
| 6440793 | Vertical MOSFET | Ramachandra Divakaruni, Heon Lee, Jack A. Mandelman, Jai-Hoon Sim | 2002-08-27 |
| 6441422 | Structure and method for ultra-scalable hybrid DRAM cell with contacted P-well | Jack A. Mandelman, Ramachandra Divakaruni, Jai-Hoon Sim | 2002-08-27 |
| 6441421 | High dielectric constant materials forming components of DRAM storage cells | Lawrence A. Clevenger, Louis L. Hsu, Joseph F. Shepard, Jr. | 2002-08-27 |
| 6440872 | Method for hybrid DRAM cell utilizing confined strap isolation | Jack A. Mandelman, Ramachandra Divakaruni, Stephan Kudelka | 2002-08-27 |
| 6437388 | Compact trench capacitor memory cell with body contact | Ulrike Gruening, Jack A. Mandelman | 2002-08-20 |
| 6429474 | Storage-capacitor electrode and interconnect | Jeffrey P. Gambino, Gary B. Bronner, David E. Kotecki | 2002-08-06 |
| 6429068 | Structure and method of fabricating embedded vertical DRAM arrays with silicided bitline and polysilicon interconnect | Ramachandra Divakaruni, Ulrike Gruening, Jack A. Mandelman, Larry Nesbit | 2002-08-06 |
| 6426252 | Silicon-on-insulator vertical array DRAM cell with self-aligned buried strap | Gary B. Bronner, Tze-Chiang Chen, Bijan Davari, Jack A. Mandelman, Dan Moy +3 more | 2002-07-30 |
| 6426526 | Single sided buried strap | Ramachandra Divakaruni, Jack A. Mandelman, Gary B. Bronner | 2002-07-30 |
| 6426251 | Process for manufacturing a crystal axis-aligned vertical side wall device | Gary B. Bronner, Ulrike Gruening, Jack A. Mandelman | 2002-07-30 |
| 6420749 | Trench field shield in trench isolation | Ramachandra Divakaruni, Jeffrey P. Gambino, Edward W. Kiewra, Jack A. Mandelman, William R. Tonti | 2002-07-16 |
| 6414347 | Vertical MOSFET | Ramachandra Divakaruni, Heon Lee, Jack A. Mandelman, Jai-Hoon Sim | 2002-07-02 |
| 6399978 | Formation of 5F2 cell with partially vertical transistor and gate conductor aligned buried strap with raised shallow trench isolation region | Ulrike Gruening | 2002-06-04 |
| 6399447 | Method of producing dynamic random access memory (DRAM) cell with folded bitline vertical transistor | Lawrence A. Clevenger, Louis L. Hsu, Jack A. Mandelman | 2002-06-04 |
| 6396096 | Design layout for a dense memory cell structure | Young Jin Park | 2002-05-28 |
| 6395594 | Method for simultaneously forming a storage-capacitor electrode and interconnect | David E. Kotecki, Jeffrey P. Gambino, Gary B. Bronner | 2002-05-28 |
| 6388294 | Integrated circuit using damascene gate structure | Mary E. Weybright, Gary B. Bronner | 2002-05-14 |
| 6380003 | Damascene anti-fuse with slot via | Christopher V. Jahnes, Chandrasekhar Narayan | 2002-04-30 |
| 6380575 | DRAM trench cell | — | 2002-04-30 |