Issued Patents 2002
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6498371 | Body-tied-to-body SOI CMOS inverter circuit | Jerry G. Fossum, Meng-Hsueh Chiang | 2002-12-24 |
| 6495887 | Argon implantation after silicidation for improved floating-body effects | Witold P. Maszara, Matthew S. Buynoski | 2002-12-17 |
| 6492209 | Selectively thin silicon film for creating fully and partially depleted SOI on same wafer | Matthew S. Buynoski, Witold P. Maszara | 2002-12-10 |
| 6466082 | Circuit technique to deal with floating body effects | — | 2002-10-15 |
| 6465847 | Semiconductor-on-insulator (SOI) device with hyperabrupt source/drain junctions | Witold P. Maszara | 2002-10-15 |
| 6462381 | Silicon-on-insulator (SOI) electrostatic discharge (ESD) protection device with backside contact opening | Stephen G. Beebe, Zoran Krivokapic | 2002-10-08 |
| 6441433 | Method of making a multi-thickness silicide SOI device | William G. En, Dong-Hyuk Ju, Bin Yu | 2002-08-27 |
| 6429083 | Removable spacer technology using ion implantation to augment etch rate differences of spacer materials | Emi Ishida, Ming-Yin Hao, Effiong Ibok | 2002-08-06 |
| 6429054 | Method of fabricating semiconductor-on-insulator (SOI) device with hyperabrupt source/drain junctions | Witold P. Maszara | 2002-08-06 |
| 6420767 | Capacitively coupled DTMOS on SOI | John C. Holst, Bin Yu | 2002-07-16 |
| 6407428 | Field effect transistor with a buried and confined metal plate to control short channel effects | Judy Xilin An | 2002-06-18 |
| 6399452 | Method of fabricating transistors with low thermal budget | Witold P. Maszara | 2002-06-04 |
| 6362063 | Formation of low thermal budget shallow abrupt junctions for semiconductor devices | Witold P. Maszara, Shekhar Pramanick | 2002-03-26 |
| 6359298 | Capacitively coupled DTMOS on SOI for multiple devices | — | 2002-03-19 |
| 6342423 | MOS-type transistor processing utilizing UV-nitride removable spacer and HF etch | Emi Ishida, Ming-Yin Hao, Effiong Ibok | 2002-01-29 |