Issued Patents 2002
Showing 1–25 of 73 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6495437 | Low temperature process to locally form high-k gate dielectrics | — | 2002-12-17 |
| 6495402 | Semiconductor-on-insulator (SOI) device having source/drain silicon-germanium regions and method of manufacture | Ralf van Bentum | 2002-12-17 |
| 6492670 | Locally confined deep pocket process for ULSI MOSFETS | — | 2002-12-10 |
| 6482705 | Method of fabricating a semiconductor device having a MOSFET with an amorphous SiGe gate electrode and an elevated crystalline SiGe source/drain structure and a device thereby formed | — | 2002-11-19 |
| 6479868 | Silicon-on-insulator transistors with asymmetric source/drain junctions formed by angled germanium implantation | Xilin Judy An, Concetta Riccobene | 2002-11-12 |
| 6479358 | Raised source/drain process by selective SiGe epitaxy | — | 2002-11-12 |
| 6475869 | Method of forming a double gate transistor having an epitaxial silicon/germanium channel region | — | 2002-11-05 |
| 6475890 | Fabrication of a field effect transistor with an upside down T-shaped semiconductor pillar in SOI technology | — | 2002-11-05 |
| 6472282 | Self-amorphized regions for transistors | — | 2002-10-29 |
| 6468888 | Method for forming polysilicon-germanium gate in CMOS transistor and device made thereby | — | 2002-10-22 |
| 6465312 | CMOS transistor with amorphous silicon elevated source-drain structure and method of fabrication | — | 2002-10-15 |
| 6465313 | SOI MOSFET with graded source/drain silicide | Ralf van Bentum | 2002-10-15 |
| 6465315 | MOS transistor with local channel compensation implant | — | 2002-10-15 |
| 6461945 | Solid phase epitaxy process for manufacturing transistors having silicon/germanium channel regions | — | 2002-10-08 |
| 6458639 | MOS transistor with stepped gate insulator | Judy Xilin An, Ming-Ren Lin | 2002-10-01 |
| 6458662 | Method of fabricating a semiconductor device having an asymmetrical dual-gate silicon-germanium (SiGe) channel MOSFET and a device thereby formed | — | 2002-10-01 |
| 6459141 | Method and apparatus for suppressing the channeling effect in high energy deep well implantation | Che-Hoo Ng | 2002-10-01 |
| 6455903 | Dual threshold voltage MOSFET by local confinement of channel depletion layer using inert ion implantation | — | 2002-09-24 |
| 6451644 | Method of providing a gate conductor with high dopant activation | — | 2002-09-17 |
| 6451656 | CMOS inverter configured from double gate MOSFET and method of fabricating same | William G. En | 2002-09-17 |
| 6448114 | Method of fabricating a silicon-on-insulator (SOI) chip having an active layer of non-uniform thickness | Judy Xilin An, William G. En | 2002-09-10 |
| 6448165 | Method for controlling the amount of trim of a gate structure of a field effect transistor | Haihong Wang | 2002-09-10 |
| 6448613 | Fabrication of a field effect transistor with minimized parasitic Miller capacitance | — | 2002-09-10 |
| 6445016 | Silicon-on-insulator (SOI) transistor having partial hetero source/drain junctions fabricated with high energy germanium implantation | Judy Xilin An | 2002-09-03 |
| 6445042 | Method and apparatus for making MOSFETs with elevated source/drain extensions | Judy Xilin An | 2002-09-03 |