Issued Patents 2002
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6500732 | Cleaving process to fabricate multilayered substrates using low implantation doses | Francois J. Henley, Michael A. Brayan | 2002-12-31 |
| 6492830 | Method and circuit for measuring charge dump of an individual transistor in an SOI device | Dong-Hyuk Ju | 2002-12-10 |
| 6458723 | High temperature implant apparatus | Francois J. Henley, Michael A. Bryan | 2002-10-01 |
| 6451656 | CMOS inverter configured from double gate MOSFET and method of fabricating same | Bin Yu | 2002-09-17 |
| 6448114 | Method of fabricating a silicon-on-insulator (SOI) chip having an active layer of non-uniform thickness | Judy Xilin An, Bin Yu | 2002-09-10 |
| 6441433 | Method of making a multi-thickness silicide SOI device | Srinath Krishnan, Dong-Hyuk Ju, Bin Yu | 2002-08-27 |
| 6433391 | Bonded SOI for floating body and metal gettering control | Dong-Hyuk Ju | 2002-08-13 |
| 6414355 | Silicon-on-insulator (SOI) chip having an active layer of non-uniform thickness | Judy Xilin An, Bin Yu | 2002-07-02 |
| 6410371 | Method of fabrication of semiconductor-on-insulator (SOI) wafer having a Si/SiGe/Si active layer | Bin Yu, Judy Xilin An, Concetta Riccobene | 2002-06-25 |
| 6399480 | Methods and arrangements for insulating local interconnects for improved alignment tolerance and size reduction | Darin A. Chan, David K. Foote, Fei Wang, Minh Van Ngo | 2002-06-04 |
| 6380588 | Semiconductor device having uniform spacers | Minh Van Ngo, Chih-Yuk Yang, David K. Foote, Scott A. Bell, Olov Karlsson +1 more | 2002-04-30 |
| 6358362 | Methods and arrangements for determining an endpoint for an in-situ local interconnect etching process | Allison Holbrook, Fei Wang | 2002-03-19 |