Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8112730 | Various methods and apparatuses for memory modeling using a structural primitive verification for memory compilers | Karen Aleksanyan, Karen Amirkhanyan, Sergey Karapetyan, Samvel Shoukourian, Valery Vardanian +1 more | 2012-02-07 |
| 7904766 | Statistical yield of a system-on-a-chip | Niranjan Behera | 2011-03-08 |
| 7692964 | Source-biased SRAM cell with reduced memory cell leakage | Deepak Sabharwal | 2010-04-06 |
| 7061794 | Wordline-based source-biasing scheme for reducing memory cell leakage | Deepak Sabharwal | 2006-06-13 |
| 7002827 | Methods and apparatuses for a ROM memory array having a virtually grounded line | Deepak Sabharwal, Izak Kense | 2006-02-21 |
| 6992938 | Methods and apparatuses for test circuitry for a dual-polarity non-volatile memory cell | Jaroslav Raszka | 2006-01-31 |
| 6646933 | Method and apparatus to reduce the amount of redundant memory column and fuses associated with a memory device | Niranjan Behera, Izak Kense | 2003-11-11 |
| 6519202 | Method and apparatus to change the amount of redundant memory column and fuses associated with a memory device | Niranjan Behera, Izak Kense | 2003-02-11 |
| 6392957 | Fast read/write cycle memory device having a self-timed read/write control circuit | Adam Kablanian, Jaroslav Raszka, Richard S. Roy | 2002-05-21 |
| 6269036 | System and method for testing multiple port memory devices | — | 2001-07-31 |
| 6051031 | Module-based logic architecture and design flow for VLSI implementation | Adam Kablanian, Vardan Duvalyan | 2000-04-18 |
| 5453636 | MOS SRAM cell with open base bipolar loads | Boaz Eitan | 1995-09-26 |
| 5402014 | Peripheral port with volatile and non-volatile configuration | Arye Ziklik, Yoram Cedar, John Pasternak | 1995-03-28 |
| 4961172 | Decoder for a memory address bus | Yoram Cedar | 1990-10-02 |
| 4939392 | Output circuit for driving a memory device output lead including a three-state inverting buffer and a transfer gate coupled between the buffer input lead and the buffer output lead | Barmak S. Sani | 1990-07-03 |