Issued Patents All Time
Showing 25 most recent of 59 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12267996 | DRAM sense amplifier architecture with reduced power consumption and related methods | Robert J. Mears | 2025-04-01 |
| 10191105 | Method for making a semiconductor device including threshold voltage measurement circuitry | — | 2019-01-29 |
| 10107854 | Semiconductor device including threshold voltage measurement circuitry | — | 2018-10-23 |
| 10109342 | Dram architecture to reduce row activation circuitry power and peripheral leakage and related methods | — | 2018-10-23 |
| 9966130 | Integrated circuit devices and methods | Lawrence T. Clark, Scott E. Thompson, Robert Rogenmoser, Damodar R. Thummalapally | 2018-05-08 |
| 9741428 | Integrated circuit devices and methods | Lawrence T. Clark, Scott E. Thompson, Robert Rogenmoser, Damodar R. Thummalapally | 2017-08-22 |
| 9449967 | Transistor array structure | Samuel Leshner | 2016-09-20 |
| 9431068 | Dynamic random access memory (DRAM) with low variation transistor peripheral circuits | Lawrence T. Clark, Lucian Shifren | 2016-08-30 |
| 9362291 | Integrated circuit devices and methods | Lawrence T. Clark, Scott E. Thompson, Robert Rogenmoser, Damodar R. Thummalapally | 2016-06-07 |
| 9342471 | High utilization multi-partitioned serial memory | Michael J. Miller | 2016-05-17 |
| 9297850 | Circuits and methods for measuring circuit elements in an integrated circuit device | Lawrence T. Clark | 2016-03-29 |
| 9117746 | Porting a circuit design from a first semiconductor process to a second semiconductor process | Lawrence T. Clark, Scott E. Thompson, Samuel Leshner | 2015-08-25 |
| 9030894 | Hierarchical multi-bank multi-port memory organization | Dipak K. Sikdar | 2015-05-12 |
| 8994415 | Multiple VDD clock buffer | — | 2015-03-31 |
| 8988153 | Ring oscillator with NMOS or PMOS variation insensitivity | — | 2015-03-24 |
| 8901747 | Semiconductor chip layout | Michael J. Miller, Mark Baumann | 2014-12-02 |
| 8890332 | Semiconductor chip layout with staggered Tx and Tx data lines | Michael J. Miller, Mark Baumann | 2014-11-18 |
| 8837230 | Circuits and methods for measuring circuit elements in an integrated circuit device | Lawrence T. Clark | 2014-09-16 |
| 8811068 | Integrated circuit devices and methods | Lawrence T. Clark, Scott E. Thompson, Robert Rogenmoser, Damodar R. Thummalapally | 2014-08-19 |
| 8806395 | Porting a circuit design from a first semiconductor process to a second semiconductor process | Lawrence T. Clark, Scott E. Thompson, Samuel Leshner | 2014-08-12 |
| 8681574 | Separate pass gate controlled sense amplifier | Dipak K. Sikdar | 2014-03-25 |
| 8645878 | Porting a circuit design from a first semiconductor process to a second semiconductor process | Lawrence T. Clark, Scott E. Thompson, Samuel Leshner | 2014-02-04 |
| 8599623 | Circuits and methods for measuring circuit elements in an integrated circuit device | Lawrence T. Clark | 2013-12-03 |
| 8547774 | Hierarchical multi-bank multi-port memory organization | Dipak K. Sikdar | 2013-10-01 |
| 8539196 | Hierarchical organization of large memory blocks | — | 2013-09-17 |