Issued Patents All Time
Showing 26–50 of 59 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8451675 | Methods for accessing DRAM cells using separate bit line control | Dipak K. Sikdar | 2013-05-28 |
| 8446755 | Multiple cycle memory write completion | — | 2013-05-21 |
| 8368217 | Integrated circuit package with segregated Tx and Rx data channels | Michael J. Miller, Mark Baumann | 2013-02-05 |
| 8139399 | Multiple cycle memory write completion | — | 2012-03-20 |
| 7859929 | Sense amplifiers | — | 2010-12-28 |
| 7379381 | State maintenance pulsing for a memory device | Farid Nemati | 2008-05-27 |
| 7319622 | Bitline shielding for thyristor-based memory | — | 2008-01-15 |
| 7158425 | System and method for providing a redundant memory array in a semiconductor memory integrated circuit | Chao-Wu Chen, Wasim Khaled | 2007-01-02 |
| 6937055 | Programmable I/O buffer | Ali Massoumi, Chao-Wu Chen | 2005-08-30 |
| 6886078 | Simultaneous access and cache loading in a hierarchically organized memory circuit | — | 2005-04-26 |
| 6678850 | Distributed interface for parallel testing of multiple devices using a single tester channel | Charles A. Miller | 2004-01-13 |
| 6664628 | Electronic component overlapping dice of unsingulated semiconductor wafer | Igor Y. Khandros, David V. Pedersen, Benjamin N. Eldridge, Gaetan L. Mathieu | 2003-12-16 |
| 6559671 | Efficient parallel testing of semiconductor devices using a known good device to generate expected responses | Charles A. Miller | 2003-05-06 |
| 6499121 | Distributed interface for parallel testing of multiple devices using a single tester channel | Charles A. Miller | 2002-12-24 |
| 6480978 | Parallel testing of integrated circuit devices using cross-DUT and within-DUT comparisons | Charles A. Miller | 2002-11-12 |
| 6466504 | Compilable block clear mechanism on per I/O basis for high-speed memory | — | 2002-10-15 |
| 6452411 | Efficient parallel testing of integrated circuit devices using a known good device to generate expected responses | Charles A. Miller | 2002-09-17 |
| 6392957 | Fast read/write cycle memory device having a self-timed read/write control circuit | Alexander Shubat, Adam Kablanian, Jaroslav Raszka | 2002-05-21 |
| 6356503 | Reduced latency row selection circuit and method | — | 2002-03-12 |
| 6330164 | Interconnect assemblies and methods including ancillary electronic component connected in immediate proximity of semiconductor device | Igor Y. Khandros, David V. Pedersen, Benjamin N. Eldridge, Gaetan L. Mathieu | 2001-12-11 |
| 6292427 | Hierarchical sense amp and write driver circuitry for compilable memory | — | 2001-09-18 |
| 6282131 | Self-timed clock circuitry in a multi-bank memory instance using a common timing synchronization node | — | 2001-08-28 |
| 6249471 | Fast full signal differential output path circuit for high-speed memory | — | 2001-06-19 |
| 6236618 | Centrally decoded divided wordline (DWL) memory architecture | — | 2001-05-22 |
| 6125421 | Independent multichannel memory architecture | — | 2000-09-26 |