| 12340865 |
Reduced circuit area memory device with a half-word memory architecture |
Harold Pilo |
2025-06-24 |
| 11670361 |
Sequential delay enabler timer circuit for low voltage operation for SRAMs |
Moon-Hae Son |
2023-06-06 |
| 11481255 |
Management of memory pages for a set of non-consecutive work elements in work queue designated by a sliding window for execution on a coherent accelerator |
Chetan L. Gaonkar, Geeta Devi Akoijam, Vamshikrishna Thatikonda |
2022-10-25 |
| 9966131 |
Using sense amplifier as a write booster in memory operating with a large dual rail voltage supply differential |
Dharmesh Kumar Sonkar |
2018-05-08 |
| 7940550 |
Systems and methods for reducing memory array leakage in high capacity memories by selective biasing |
Deepak Sabharwal, Yong Zhang |
2011-05-10 |
| 7904766 |
Statistical yield of a system-on-a-chip |
Alexander Shubat |
2011-03-08 |
| 7788551 |
System and method for repairing a memory |
Bruce L. Prickett, Jr., Yervant Zorian |
2010-08-31 |
| 7539590 |
System and method for testing a memory |
Bruce L. Prickett, Jr. |
2009-05-26 |
| 7415641 |
System and method for repairing a memory |
Bruce L. Prickett, Jr., Yervant Zorian |
2008-08-19 |
| 7139204 |
Method and system for testing a dual-port memory at speed in a stressed environment |
— |
2006-11-21 |
| 7031866 |
System and method for testing a memory |
Bruce L. Prickett, Jr. |
2006-04-18 |
| 6646933 |
Method and apparatus to reduce the amount of redundant memory column and fuses associated with a memory device |
Alexander Shubat, Izak Kense |
2003-11-11 |
| 6519202 |
Method and apparatus to change the amount of redundant memory column and fuses associated with a memory device |
Alexander Shubat, Izak Kense |
2003-02-11 |
| 6396760 |
Memory having a redundancy scheme to allow one fuse to blow per faulty memory column |
Shreekanth Sampigethaya |
2002-05-28 |