Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9898568 | Reducing the load on the bitlines of a ROM bitcell array | Naveen Chandra Srivastava, Janardhan Achanta, Pankaj Kumar | 2018-02-20 |
| 9710589 | Using a cut mask to form spaces representing spacing violations in a semiconductor structure | Kalpeshkumar Girishchandra Dave, Naveen Chandra Srivastava, Pankaj Kumar, Janardhan Achanta | 2017-07-18 |
| 9509255 | Offset compensation for sense amplifiers | Bharath Upputuri | 2016-11-29 |
| 9322859 | Offset compensation for sense amplifiers | Bharath Upputuri | 2016-04-26 |
| 8630134 | Memory cells having a row-based read and/or write support circuitry | Bharath Upputuri | 2014-01-14 |
| 8362807 | Offset compensation for sense amplifiers | Bharath Upputuri | 2013-01-29 |
| 8213242 | Memory cells having a row-based read and/or write support circuitry | Bharath Upputuri | 2012-07-03 |
| 7251186 | Multi-port memory utilizing an array of single-port memory cells | Subramani Kengeri, Deepak Sabharwal, Prakash Bhatia, Sanjiv Kainth | 2007-07-31 |
| 6396760 | Memory having a redundancy scheme to allow one fuse to blow per faulty memory column | Niranjan Behera | 2002-05-28 |