Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9898568 | Reducing the load on the bitlines of a ROM bitcell array | Janardhan Achanta, Pankaj Kumar, Shreekanth Sampigethaya | 2018-02-20 |
| 9710589 | Using a cut mask to form spaces representing spacing violations in a semiconductor structure | Kalpeshkumar Girishchandra Dave, Pankaj Kumar, Janardhan Achanta, Shreekanth Sampigethaya | 2017-07-18 |
| 7900174 | Method and system for characterizing an integrated circuit design | Rajiv Shankar, Kousik Mukherjee, Shelly Adhikari, Richa Gupta, Rajat Chopra | 2011-03-01 |