KA

Karen Aleksanyan

SY Synopsys: 3 patents #460 of 2,302Top 20%
VL Virage Logic: 1 patents #44 of 67Top 70%
Overall (All Time): #1,224,250 of 4,157,543Top 30%
4
Patents All Time

Issued Patents All Time

Showing 1–4 of 4 patents

Patent #TitleCo-InventorsDate
8359553 Various methods and apparatuses for effective yield enhancement of good chip dies having memories per wafer Valery Vardanian, Yervant Zorian 2013-01-22
8112730 Various methods and apparatuses for memory modeling using a structural primitive verification for memory compilers Karen Amirkhanyan, Sergey Karapetyan, Alexander Shubat, Samvel Shoukourian, Valery Vardanian +1 more 2012-02-07
7890900 Various methods and apparatuses for effective yield enhancement of good chip dies having memories per wafer Valery Vardanian, Yervant Zorian 2011-02-15
7768840 Memory modeling using an intermediate level structural description Karen Amirkhanyan, Samvel Shoukourian, Valery Vardanian, Yervant Zorian 2010-08-03