Issued Patents All Time
Showing 76–100 of 118 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7464088 | Architecture for efficient pattern match operations | — | 2008-12-09 |
| 7024808 | Neon sign arrangement | — | 2006-04-11 |
| 6255845 | Efficient use of spare gates for post-silicon debug and enhancements | Jacques Wong, Jaime Tolentino | 2001-07-03 |
| 6172519 | Bus-hold circuit having a defined state during set-up of an in-system programmable device | Jesse H. Jenkins, IV, Robert Olah | 2001-01-09 |
| 6018250 | Programming method to enable system recovery after power failure | Neil G. Jacobson | 2000-01-25 |
| 5898602 | Carry chain circuit with flexible carry function for implementing arithmetic and logical functions | Daniel J. Rothman | 1999-04-27 |
| 5784577 | Automated control system for programming PLDs | Neil G. Jacobson | 1998-07-21 |
| 5764076 | Circuit for partially reprogramming an operational programmable logic device | Napoleon W. Lee, Derek R. Curd, Jeffrey H. Seltzer, Jeffrey Goldberg, Kameswara K. Rao +1 more | 1998-06-09 |
| 5742178 | Programmable voltage stabilizing circuit for a programmable integrated circuit device | Jesse H. Jenkins, IV, Nicholas Kucharewski | 1998-04-21 |
| 5570051 | Multiplexed by-passable memory devices with increased speed and improved flip-flop utilization | Napoleon W. Lee, Thomas Y. Ho, Nicholas Kucharewski | 1996-10-29 |
| 5565792 | Macrocell with product-term cascade and improved flip flop utilization | Napoleon W. Lee, Thomas Y. Ho, David Harrison, Nicholas Kucharewski, Jeffrey H. Seltzer | 1996-10-15 |
| 5530378 | Cross point interconnect structure with reduced area | Nicholas Kucharewski, Jesse H. Jenkins, IV | 1996-06-25 |
| 5506878 | Programmable clock having programmable delay and duty cycle based on a user-supplied reference clock | — | 1996-04-09 |
| 5506518 | Antifuse-based programmable logic circuit | — | 1996-04-09 |
| 5506523 | Sense circuit with selectable zero power single input function mode | Nicholas Kucharewski | 1996-04-09 |
| 5486776 | Antifuse-based programmable logic circuit | — | 1996-01-23 |
| 5483478 | Method and structure for reducing carry delay for a programmable carry chain | — | 1996-01-09 |
| 5450021 | EPLD chip with hybrid architecture optimized for both speed and flexibility | — | 1995-09-12 |
| 5448181 | Output buffer circuit having reduced switching noise | — | 1995-09-05 |
| 5384499 | High-density erasable programmable logic device architecture using multiplexer interconnections | Bruce B. Pedersen, Francis B. Heile, Cameron McClintock, Hock C. So, James A. Watson | 1995-01-24 |
| 5362999 | EPLD chip with hybrid architecture optimized for both speed and flexibility | — | 1994-11-08 |
| 5361229 | Precharging bitlines for robust reading of latch data | Wei-Yi Ku | 1994-11-01 |
| 5357153 | Macrocell with product-term cascade and improved flip flop utilization | Napoleon W. Lee, Thomas Y. Ho, David Harrison, Nicholas Kucharewski, Jeffrey H. Seltzer | 1994-10-18 |
| 5349249 | Programmable logic device having security elements located amongst configuration bit location to prevent unauthorized reading | Thomas Y. Ho, Wei-Yi Ku, George H. Simmons, Robert W. Barker, II | 1994-09-20 |
| 5332929 | Power management for programmable logic devices | — | 1994-07-26 |