Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6518148 | Method for protecting STI structures with low etching rate liners | Chien-Li Cheng, Kern-Huat Ang | 2003-02-11 |
| 6187668 | Method of forming self-aligned unlanded via holes | Hua-Shu Wu, Hung-Chan Lin | 2001-02-13 |
| 6080674 | Method for forming via holes | Hua-Shu Wu | 2000-06-27 |
| 6004851 | Method for manufacturing MOS device with adjustable source/drain extensions | — | 1999-12-21 |
| 5986310 | Prolonging a polysilicon layer in smaller memory cells to prevent polysilicon load punch through | — | 1999-11-16 |
| 5977598 | High load resistance implemented in a separate polysilicon layer with diffusion barrier therein for preventing load punch through therefrom | Chih-Ming Chen, Wen-Ying Wen | 1999-11-02 |
| 5910452 | Method for reducing antenna effect during plasma etching procedure for semiconductor device fabrication | Tzong-Kuei Kang, Huang-Chung Cheng, Chun-Hsing Shih | 1999-06-08 |