Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11287873 | Sensing device and control method | Tsung-Ta Chen, Tien-Yu Lin | 2022-03-29 |
| 7923325 | Deep trench device with single sided connecting structure and fabrication method thereof | Shian-Jyh Lin | 2011-04-12 |
| 7897501 | Method of fabricating a field-effect transistor having robust sidewall spacers | Sun-Jay Chang, Tung-Heng Hsieh, Yung-Shen Chen | 2011-03-01 |
| 7795090 | Electrical device and method for fabricating the same | Shian-Jyh Lin, Pei-Ing Lee, Chung-Yuan Lee | 2010-09-14 |
| 7679137 | Method for fabricating recessed gate MOS transistor device | Pei-Ing Lee, Shian-Jyh Lin | 2010-03-16 |
| 7638391 | Semiconductor memory device and fabrication method thereof | Shian-Jyh Lin, Ming-Yuan Huang | 2009-12-29 |
| 7619271 | Deep trench device with single sided connecting structure and fabrication method thereof | Shian-Jyh Lin | 2009-11-17 |
| 7592233 | Method for forming a memory device with a recessed gate | Pei-Ing Lee, Chung-Yuan Lee | 2009-09-22 |
| 7563686 | Method for forming a memory device with a recessed gate | Pei-Ing Lee, Chung-Yuan Lee | 2009-07-21 |
| 7535045 | Checkerboard deep trench dynamic random access memory cell array layout | Chin-Tien Yang, Tzung-Han Lee, Shian-Hau Liao, Chung-Yuan Lee | 2009-05-19 |
| 7473598 | Method for forming stack capacitor | Shian-Hau Liao, Tsung-Shin Wu, Chih-Chiang Kuo | 2009-01-06 |
| 7446355 | Electrical device and method for fabricating the same | Shian-Jyh Lin, Pei-Ing Lee, Chung-Yuan Lee | 2008-11-04 |
| 7382028 | Method for forming silicide and semiconductor device formed thereby | Tung-Heng Hsieh, Yi-Shien Mor, Yung-Shun Chen | 2008-06-03 |
| 7316978 | Method for forming recesses | Pei-Ing Lee, Chung-Yuan Lee | 2008-01-08 |
| 7190033 | CMOS device and method of manufacture | Sun-Jay Chang | 2007-03-13 |
| 7179748 | Method for forming recesses | Pei-Ing Lee, Chung-Yuan Lee | 2007-02-20 |
| 6518148 | Method for protecting STI structures with low etching rate liners | Kern-Huat Ang, Chun-Hung Peng | 2003-02-11 |