Issued Patents All Time
Showing 26–50 of 114 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10312207 | Passivation scheme for pad openings and trenches | Ming-Hong Chang, Chun-Yi Yang, Kun-Ming Huang, Po-Tao Chu, Shen-Ping Wang | 2019-06-04 |
| 10276651 | Low warpage high density trench capacitor | Jyun-Ying Lin, Hsin-Li Cheng, Jing-Hwang Yang, Felix Ying-Kit Tsui | 2019-04-30 |
| 10199273 | Method for forming semiconductor device with through silicon via | Yung-Chang Lin | 2019-02-05 |
| 10163707 | Method for forming group III-V device structure | Ming-Hong Chang, Hsin-Chih Lin, Shen-Ping Wang, Chung-Cheng Chen, Po-Tao Chu | 2018-12-25 |
| 10134867 | Method for fabricating semiconductor device | Jheng-Sheng YOU, Hsin-Chih Lin, Kun-Ming Huang, Lieh-Chuan Chen, Po-Tao Chu +1 more | 2018-11-20 |
| 9947640 | Wafer, package structure and method of manufacturing the same | — | 2018-04-17 |
| 9941384 | Semiconductor device and method for fabricating the same | Jheng-Sheng YOU, Hsin-Chih Lin, Kun-Ming Huang, Lieh-Chuan Chen, Po-Tao Chu +1 more | 2018-04-10 |
| 9929081 | Interposer fabricating process | — | 2018-03-27 |
| 9704841 | Method of packaging stacked dies on wafer using flip-chip bonding | — | 2017-07-11 |
| 9698122 | Semiconductor package structure and method for manufacturing the same | — | 2017-07-04 |
| 9666507 | Through-substrate structure and method for fabricating the same | Chun-Hung Chen, Ming-Tse Lin | 2017-05-30 |
| 9478499 | Semiconductor package structure and method for manufacturing the same | — | 2016-10-25 |
| 9466560 | Interposer fabricating process and wafer packaging structure | — | 2016-10-11 |
| 9437491 | Method of forming chip with through silicon via electrode | Ming-Tse Lin, Chu-Fu Lin, Yung-Chang Lin | 2016-09-06 |
| 9412686 | Interposer structure and manufacturing method thereof | Ming-Tse Lin, Kuei-Sheng Wu | 2016-08-09 |
| 9343359 | Integrated structure and method for fabricating the same | Chun-Hung Chen, Ming-Tse Lin, Yung-Chang Lin | 2016-05-17 |
| 9287173 | Through silicon via and process thereof | Chun-Hung Chen, Ming-Tse Lin, Yung-Chang Lin | 2016-03-15 |
| 9275933 | Semiconductor device | Yung-Chang Lin | 2016-03-01 |
| 9269645 | Fan-out wafer level package | Chu-Fu Lin, Kuo-Ming Chen | 2016-02-23 |
| 9123789 | Chip with through silicon via electrode and method of forming the same | Ming-Tse Lin, Chu-Fu Lin, Yung-Chang Lin | 2015-09-01 |
| 9123730 | Semiconductor device having through silicon trench shielding structure surrounding RF circuit | Yung-Chang Lin, Ming-Tse Lin, Kuei-Sheng Wu, Chia-Fang Lin | 2015-09-01 |
| 9117804 | Interposer structure and manufacturing method thereof | — | 2015-08-25 |
| 9048223 | Package structure having silicon through vias connected to ground potential | Yung-Chang Lin, Ming-Tse Lin | 2015-06-02 |
| 9024416 | Semiconductor structure | Chun-Hung Chen, Ming-Tse Lin, Kuei-Sheng Wu | 2015-05-05 |
| 9012324 | Through silicon via process | Jia-Jia Chen, Chi-Mao Hsu, Tsun-Min Cheng, Ching-Wei Hsu, Szu-Hao Lai +3 more | 2015-04-21 |