Issued Patents All Time
Showing 26–49 of 49 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8476127 | Integrated lateral high voltage MOSFET | Marie Denison, Sameer Pendharkar | 2013-07-02 |
| 8461589 | Circuit having integrated heating structure for parametric trimming | Barry Jon Male, Wilburn M. Miller | 2013-06-11 |
| 8278683 | Lateral insulated gate bipolar transistor | Hideaki Kawahara | 2012-10-02 |
| 8274131 | Isolation trench with rounded corners for BiCMOS process | Sameer Pendharkar, John Lin, Steven L. Merchant | 2012-09-25 |
| 7989853 | Integration of high voltage JFET in linear bipolar CMOS process | Pinghai Hao, Sameer Pendharkar, Marie Denison | 2011-08-02 |
| 7910417 | Distributed high voltage JFET | David A. Walch, John Lin, Steven L. Merchant | 2011-03-22 |
| 7846789 | Isolation trench with rounded corners for BiCMOS process | Sameer Pendharkar, John Lin, Steven L. Merchant | 2010-12-07 |
| 7741205 | Integrated circuit having a top side wafer contact and a method of manufacture therefor | Tony Phan, William Loftin, John Lin | 2010-06-22 |
| 7736961 | High voltage depletion FET employing a channel stopping implant | Steven L. Merchant, Scott Paiva | 2010-06-15 |
| 7605412 | Distributed high voltage JFET | David A. Walch, John Lin, Steven L. Merchant | 2009-10-20 |
| 7417270 | Distributed high voltage JFET | David A. Walch, John Lin, Steven L. Merchant | 2008-08-26 |
| 7345343 | Integrated circuit having a top side wafer contact and a method of manufacture therefor | Tony Phan, William Loftin, John Lin | 2008-03-18 |
| 7268045 | N-channel LDMOS with buried P-type region to prevent parasitic bipolar effects | Taylor R. Efland | 2007-09-11 |
| 7262109 | Integrated circuit having a transistor level top side wafer contact and a method of manufacture therefor | John Lin, Tony Phan, William Loftin, Martin B. Mollat | 2007-08-28 |
| 7195965 | Premature breakdown in submicron device geometries | John Lin, Taylor R. Efland, Sameer Pendharkar, Vladimir Bolkhovsky | 2007-03-27 |
| 7187034 | Distributed power MOSFET | John Lin, Sameer Pendharkar, Steven L. Merchant | 2007-03-06 |
| 6958515 | N-channel LDMOS with buried p-type region to prevent parasitic bipolar effects | Taylor R. Efland | 2005-10-25 |
| 6878999 | Transistor with improved safe operating area | John Lin, Sameer Pendharkar, Steven L. Jensen | 2005-04-12 |
| 6815276 | Segmented power MOSFET of safe operation | John Lin, Sameer Pendharkar, Steven L. Merchant | 2004-11-09 |
| 6624481 | ESD robust bipolar transistor with high variable trigger and sustaining voltages | Sameer Pendharkar, Robert Steinhoff | 2003-09-23 |
| 5164813 | New diode structure | Scott C. Blackstone, Elizabeth M. Roughan, Christopher Doucette, Roy Lee, Carolyn Q. Cotnam | 1992-11-17 |
| 4901120 | Structure for fast-recovery bipolar devices | Carson E. Weaver | 1990-02-13 |
| 4551353 | Method for reducing leakage currents in semiconductor devices | Eric Li | 1985-11-05 |
| 4231059 | Technique for controlling emitter ballast resistance | Derrick J. Page | 1980-10-28 |