Issued Patents All Time
Showing 76–100 of 103 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11226822 | Look-up table initialize | Dheera Balasubramanian Samudrala, Duc Quang Bui, Rama Venkatasubramanian | 2022-01-18 |
| 11194729 | Victim cache that supports draining write-miss entries | Timothy David Anderson, Pete Michael Hippleheuser | 2021-12-07 |
| 11157278 | Histogram operation | Duc Quang Bui, Rama Venkatasubramanian, Dheera Balasubramanian Samudrala, Alan L. Davis | 2021-10-26 |
| 11144456 | Hardware coherence signaling protocol | Abhijeet Ashok Chachad, David Matthew Thompson, Peter Michael Hippleheuser | 2021-10-12 |
| 11119935 | Methods and apparatus to facilitate atomic compare and swap in cache for a coherent level 1 data cache system | Timothy David Anderson, Pete Michael Hippleheuser | 2021-09-14 |
| 11106583 | Shadow caches for level 2 cache controller | Abhijeet Ashok Chachad, David Matthew Thompson | 2021-08-31 |
| 11106584 | Hardware coherence for memory controller | Abhijeet Ashok Chachad, David Matthew Thompson | 2021-08-31 |
| 11036648 | Highly integrated scalable, flexible DSP megamodule architecture | Timothy David Anderson, Joseph Zbiciak, Duc Quang Bui, Abhijeet Ashok Chachad, Kai Chirca +3 more | 2021-06-15 |
| 10963255 | Implied fence on stream open | Kai Chirca, Timothy David Anderson, Duc Quang Bui, Abhijeet Ashok Chachad, Son Hung Tran | 2021-03-30 |
| 10761850 | Look up table with data element promotion | Duc Quang Bui, Dheera Balasubramanian, Sahithi KRISHNA | 2020-09-01 |
| 10162641 | Highly integrated scalable, flexible DSP megamodule architecture | Timothy David Anderson, Joseph Zbiciak, Duc Quang Bui, Abhijeet Ashok Chachad, Kai Chirca +3 more | 2018-12-25 |
| 9965395 | Memory attribute sharing between differing cache levels of multilevel cache | Raguram Damodaran, Joseph Zbiciak | 2018-05-08 |
| 9606803 | Highly integrated scalable, flexible DSP megamodule architecture | Timothy David Anderson, Joseph Zbiciak, Duc Quang Bui, Abhijeet Ashok Chachad, Kai Chirca +3 more | 2017-03-28 |
| 9575901 | Programmable address-based write-through cache control | Raguram Damodaran, Abhijeet Ashok Chachad, David Matthew Thompson | 2017-02-21 |
| 9557936 | Protection of memories, datapath and pipeline registers, and other storage elements by distributed delayed detection and correction of soft errors | Timothy David Anderson, Joseph Zbiciak, Abhijeet Ashok Chachad, Kai Chirca, David Matthew Thompson +2 more | 2017-01-31 |
| 9390011 | Zero cycle clock invalidate operation | Raguram Damodaran, Abhijeet Ashok Chachad | 2016-07-12 |
| 9244837 | Zero cycle clock invalidate operation | Raguram Damodaran, Abhijeet Ashok Chachad | 2016-01-26 |
| 9189331 | Programmable address-based write-through cache control | Raguram Damodaran, Abhijeet Ashok Chachad | 2015-11-17 |
| 9183084 | Memory attribute sharing between differing cache levels of multilevel cache | Raguram Damodaran, Joseph Zbiciak | 2015-11-10 |
| 9021320 | pBIST architecture with multiple asynchronous sub chips operating in differing voltage domains | Raguram Damodaran, Aman Kokrady | 2015-04-28 |
| 9009550 | pBIST engine with distributed data logging | Raguram Damodaran, Aman Kokrady | 2015-04-14 |
| 8977821 | Parallel processing of multiple block coherence operations | Raguram Damodaran | 2015-03-10 |
| 8977915 | pBIST engine with reduced SRAM testing bus width | Raguram Damodaran, Aman Kokrady | 2015-03-10 |
| 8930783 | pBIST read only memory image compression | Raguram Damodaran, Aman Kokrady | 2015-01-06 |
| 8904249 | At speed testing of high performance memories with a multi-port BIS engine | Raguram Damodaran | 2014-12-02 |