Issued Patents All Time
Showing 26–50 of 103 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12105640 | Methods and apparatus for eviction in dual datapath victim cache system | Timothy David Anderson, Pete Michael Hippleheuser | 2024-10-01 |
| 12093690 | Look-up table read | Dheera Balasubramanian Samudrala, Duc Quang Bui, Alan L. Davis | 2024-09-17 |
| 12086064 | Aliased mode for cache controller | Abhijeet Ashok Chachad, Timothy David Anderson, Pramod Kumar Swami, David Matthew Thompson, Neelima Muralidharan | 2024-09-10 |
| 12072814 | Methods and apparatus to facilitate read-modify-write support in a victim cache | Timothy David Anderson, Pete Michael Hippleheuser | 2024-08-27 |
| 12072812 | Highly integrated scalable, flexible DSP megamodule architecture | Timothy David Anderson, Joseph Zbiciak, Duc Quang Bui, Abhijeet Ashok Chachad, Kai Chirca +3 more | 2024-08-27 |
| 12056051 | Tag update bus for updated coherence state | Abhijeet Ashok Chachad, David Matthew Thompson, Peter Michael Hippleheuser | 2024-08-06 |
| 12038840 | Multi-level cache security | Abhijeet Ashok Chachad, David Matthew Thompson | 2024-07-16 |
| 12007907 | Victim cache with write miss merging | Timothy David Anderson, Pete Michael Hippleheuser | 2024-06-11 |
| 12001345 | Victim cache that supports draining write-miss entries | Timothy David Anderson, Pete Michael Hippleheuser | 2024-06-04 |
| 11960891 | Look-up table write | Duc Quang Bui, Dheera Balasubramanian Samudrala | 2024-04-16 |
| 11940929 | Methods and apparatus to reduce read-modify-write cycles for non-aligned writes | Timothy David Anderson, Pete Michael Hippleheuser | 2024-03-26 |
| 11940930 | Methods and apparatus to facilitate atomic operations in victim cache | Timothy David Anderson, Pete Michael Hippleheuser | 2024-03-26 |
| 11886353 | Hybrid victim cache and write miss buffer with fence operation | Timothy David Anderson, Pete Michael Hippleheuser | 2024-01-30 |
| 11868272 | Methods and apparatus for allocation in a victim cache system | Timothy David Anderson, Pete Michael Hippleheuser | 2024-01-09 |
| 11816032 | Cache size change | Abhijeet Ashok Chachad, David Matthew Thompson, Neelima Muralidharan | 2023-11-14 |
| 11803486 | Write merging on stores with different privilege levels | Timothy David Anderson, Pete Michael Hippleheuser | 2023-10-31 |
| 11803382 | Look-up table read | Duc Quang Bui, Dheera Balasubramanian Samudrala, Rama Venkatasubramanian | 2023-10-31 |
| 11789868 | Hardware coherence signaling protocol | Abhijeet Ashok Chachad, David Matthew Thompson, Pete Michael Hippleheuser | 2023-10-17 |
| 11782718 | Implied fence on stream open | Kai Chirca, Timothy David Anderson, Duc Quang Bui, Abhijeet Ashok Chachad, Son Hung Tran | 2023-10-10 |
| 11775446 | Methods and apparatus to facilitate atomic compare and swap in cache for a coherent level 1 data cache system | Timothy David Anderson, Pete Michael Hippleheuser | 2023-10-03 |
| 11775302 | Histogram operation | Duc Quang Bui, Rama Venkatasubramanian, Dheera Balasubramanian Samudrala, Alan L. Davis | 2023-10-03 |
| 11762780 | Write merging on stores with different tags | Timothy David Anderson, Pete Michael Hippleheuser | 2023-09-19 |
| 11741020 | Methods and apparatus to facilitate fully pipelined read-modify-write support in level 1 data cache using store queue and data forwarding | Timothy David Anderson, Pete Michael Hippleheuser | 2023-08-29 |
| 11740930 | Global coherence operations | Abhijeet Ashok Chachad, David Matthew Thompson, Neelima Muralidharan | 2023-08-29 |
| 11720495 | Multi-level cache security | Abhijeet Ashok Chachad, David Matthew Thompson | 2023-08-08 |