Issued Patents All Time
Showing 25 most recent of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9030216 | Coaxial four-point probe for low resistance measurements | Siva Prakash Gurrum, Rajiv Dunne | 2015-05-12 |
| 8174276 | Coaxial four-point probe for low resistance measurements | Siva Prakash Gurrum, Rajiv Dunne | 2012-05-08 |
| 7795072 | Structure and method of high performance two layer ball grid array substrate | Navinchandra Kalidas | 2010-09-14 |
| 7265443 | Wire bonded semiconductor device having low inductance and noise | Howard R. Test | 2007-09-04 |
| 7195954 | Low capacitance coupling wire bonded semiconductor device | Homer B. Klonis | 2007-03-27 |
| 7132845 | FA tool using conductor model | Jay Michael Lawyer, Roger J. Stierman | 2006-11-07 |
| 7132740 | Semiconductor package with conductor impedance selected during assembly | Heping Yue | 2006-11-07 |
| 6995037 | Structure and method of high performance two layer ball grid array substrate | Navinchandra Kalidas | 2006-02-07 |
| 6822340 | Low capacitance coupling wire bonded semiconductor device | Homer B. Klonis | 2004-11-23 |
| 6820046 | System for electrically modeling an electronic structure and method of operation | Subhendu Kundu, Ramani Ramesh | 2004-11-16 |
| 6794743 | Structure and method of high performance two layer ball grid array substrate | Navinchandra Kalidas | 2004-09-21 |
| 6563208 | Semiconductor package with conductor impedance selected during assembly | Heping Yue | 2003-05-13 |
| 6518663 | Constant impedance routing for high performance integrated circuit packaging | Richard D. James | 2003-02-11 |
| 6424027 | Low pass filter integral with semiconductor package | Heping Yue, Truong Ho | 2002-07-23 |
| 6323116 | Differential pair geometry for integrated circuit chip packages | — | 2001-11-27 |
| 6084777 | Ball grid array package | Navinchandra Kalidas, Nozar Hassanzadeh | 2000-07-04 |
| 6064576 | Interposer having a cantilevered ball connection and being electrically connected to a printed circuit board | Darvin R. Edwards | 2000-05-16 |
| 6054758 | Differential pair geometry for integrated circuit chip packages | — | 2000-04-25 |
| 6030859 | Method of making a packaged semiconductor device and a lead-frame therefor | Ichiro Anjoh, Gen Murakami, Katherine G. Heinen | 2000-02-29 |
| 5994169 | Lead frame for integrated circuits and process of packaging | Katherine G. Heinen | 1999-11-30 |
| 5840599 | Process of packaging an integrated circuit with a conductive material between a lead frame and the face of the circuit | Katherine G. Heinen | 1998-11-24 |
| 5648299 | Packaged semiconductor device and a leadframe therefor | Ichiro Anjoh, Gen Murakami, Katherine G. Heinen | 1997-07-15 |
| 5585665 | Packaged semiconductor device and a leadframe therefor | Ichiro Anjoh, Gen Murakami, Katherine G. Heinen | 1996-12-17 |
| 5442233 | Packaged semiconductor device and a lead frame therefor, having a common potential lead with lead portions having dual functions of chip support and heat dissipation | Ichiro Anjoh, Gen Murakami, Katherine G. Heinen | 1995-08-15 |
| 5432127 | Method for making a balanced capacitance lead frame for integrated circuits having a power bus and dummy leads | Katherine G. Heinen | 1995-07-11 |