Issued Patents All Time
Showing 76–97 of 97 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10871965 | System and method to control the number of active vector lanes in a processor | Timothy David Anderson | 2020-12-22 |
| 10761850 | Look up table with data element promotion | Dheera Balasubramanian, Naveen Bhoria, Sahithi KRISHNA | 2020-09-01 |
| 10747636 | Streaming engine with deferred exception reporting | Joseph Zbiciak, Timothy David Anderson, Kai Chirca | 2020-08-18 |
| 10732689 | Controlling the number of powered vector lanes via a register field | Timothy David Anderson | 2020-08-04 |
| 10628156 | Vector SIMD VLIW data path architecture | Timothy David Anderson, Mujibur Rahman, Joseph Zbiciak, Eric Biscondi, Peter Richard Dent +2 more | 2020-04-21 |
| 10620957 | Method for forming constant extensions in the same execute packet in a VLIW processor | Timothy David Anderson, Joseph Zbiciak | 2020-04-14 |
| 10530397 | Butterfly network on load data return | Dheera Balasubramanian, Joseph Zbiciak, Timothy David Anderson | 2020-01-07 |
| 10423413 | Vector load and duplicate operations | Timothy David Anderson, Peter Richard Dent | 2019-09-24 |
| 10402199 | Conditional execution specification of instructions using conditional extension slots in the same execute packet in a VLIW processor | Timothy David Anderson, Joseph Zbiciak | 2019-09-03 |
| 10318293 | Predication methods for vector processors | Timothy David Anderson, Joseph Zbiciak | 2019-06-11 |
| 10175981 | Method to control the number of active vector lanes for power efficiency | Timothy David Anderson | 2019-01-08 |
| 10162641 | Highly integrated scalable, flexible DSP megamodule architecture | Timothy David Anderson, Joseph Zbiciak, Abhijeet Ashok Chachad, Kai Chirca, Naveen Bhoria +3 more | 2018-12-25 |
| 10061675 | Streaming engine with deferred exception reporting | Joseph Zbiciak, Timothy David Anderson, Kai Chirca | 2018-08-28 |
| 10007518 | Register file structures combining vector and scalar data with global and local accesses | Timothy David Anderson, Mel Alan Phipps, Todd T. Hahn, Joseph Zbiciak | 2018-06-26 |
| 9606803 | Highly integrated scalable, flexible DSP megamodule architecture | Timothy David Anderson, Joseph Zbiciak, Abhijeet Ashok Chachad, Kai Chirca, Naveen Bhoria +3 more | 2017-03-28 |
| 9489197 | Highly efficient different precision complex multiply accumulate to enhance chip rate functionality in DSSS cellular systems | Mujibur Rahman, Peter Richard Dent, Timothy David Anderson | 2016-11-08 |
| 9239735 | Compiler-control method for load speculation in a statically scheduled microprocessor | Timothy David Anderson, Joseph Zbiciak, Mel Alan Phipps, Todd T. Hahn | 2016-01-19 |
| 8880855 | Dual register data path architecture with registers in a data file divided into groups and sub-groups | Timothy David Anderson, Eric Biscondi, Shriram D. Moharil, Mujibur Rahman, Soujanya Narnur +2 more | 2014-11-04 |
| 8572154 | Reduced-level two's complement arithmetic unit | Timothy David Anderson | 2013-10-29 |
| 6128687 | Fast fault detection circuitry for a microprocessor | Tuan Dao | 2000-10-03 |
| 5991863 | Single carry/borrow propagate adder/decrementer for generating register stack addresses in a microprocessor | Tuan Dao, Debjit Das Sarma | 1999-11-23 |
| 5771366 | Method and system for interchanging operands during complex instruction execution in a data processing system | Andrew A. Bjorksten, Richard E. Fry, James E. Phillips | 1998-06-23 |