Issued Patents All Time
Showing 76–100 of 124 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9899387 | Multi-gate device and method of fabrication thereof | Kuo-Cheng Ching, Chung-Cheng Wu, Ching-Fang Huang, Wen-Hsing Hsieh, Cheng-Ting Chung | 2018-02-20 |
| 9899269 | Multi-gate device and method of fabrication thereof | Kuo-Cheng Ching, Ching-Wei Tsai, Carlos H. Diaz, Chih-Hao Wang, Wai-Yi Lien | 2018-02-20 |
| 9887269 | Multi-gate device and method of fabrication thereof | Kuo-Cheng Ching, Ching-Fang Huang, Carlos H. Diaz, Chih-Hao Wang, Wen-Hsing Hsieh | 2018-02-06 |
| 9876108 | Wrap around silicide for FinFETs | Kuo-Cheng Ching, Chi-Wen Liu | 2018-01-23 |
| 9847425 | FinFET with a semiconductor strip as a base | Kuo-Cheng Ching, Shi Ning Ju, Ching-Wei Tsai, Chih-Hao Wang, Carlos H. Diaz | 2017-12-19 |
| 9818867 | Simple and cost-free MTP structure | Shyue Seng Tan, Yuan-Chen Sun, Eng Huat Toh, Kiok Boone Elgin Quek | 2017-11-14 |
| 9818872 | Multi-gate device and method of fabrication thereof | Kuo-Cheng Ching, Ching-Wei Tsai, Carlos H. Diaz, Chih-Hao Wang, Wai-Yi Lien | 2017-11-14 |
| 9773705 | FinFET channel on oxide structures and related methods | Kuo-Cheng Ching, Ching-Wei Tsai | 2017-09-26 |
| 9741821 | Two-step dummy gate formation | Kuo-Cheng Ching, Kuan-Ting Pan, Chih-Hao Wang, Carlos H. Diaz | 2017-08-22 |
| 9716096 | Semiconductor structure with feature spacer and method for manufacturing the same | Kuo-Cheng Ching, Chun-Hsiung Lin, Chih-Hao Wang, Carlos H. Diaz | 2017-07-25 |
| 9711533 | FinFET devices having different source/drain proximities for input/output devices and non-input/output devices and the method of fabrication thereof | Kuo-Cheng Ching, Ching-Wei Tsai, Chih-Hao Wang | 2017-07-18 |
| 9666581 | FinFET with source/drain structure and method of fabrication thereof | Kuo-Cheng Ching, Ching-Wei Tsai | 2017-05-30 |
| 9614027 | High voltage transistor with reduced isolation breakdown | Shyue Seng Tan | 2017-04-04 |
| 9608116 | FINFETs with wrap-around silicide and method forming the same | Kuo-Cheng Ching, Ching-Wei Tsai, Chi-Wen Liu, Chih-Hao Wang | 2017-03-28 |
| 9559184 | Devices including gate spacer with gap or void and methods of forming the same | Kuo-Cheng Ching, Ching-Wei Tsai, Chi-Wen Liu | 2017-01-31 |
| 9508858 | Contacts for highly scaled transistors | Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Jean-Pierre Colinge +2 more | 2016-11-29 |
| 9418897 | Wrap around silicide for FinFETs | Kuo-Cheng Ching, Chi-Wen Liu | 2016-08-16 |
| 9368386 | Corner transistor suppression | Shyue Seng Tan, Elgin Quek | 2016-06-14 |
| 9029227 | P-channel flash with enhanced band-to-band tunneling hot electron injection | Eng Huat Toh, Elgin Quek, Sanford Chu | 2015-05-12 |
| 8957470 | Integration of memory, high voltage and logic devices | Yan Tang, Shyue Seng Tan, Elgin Quek | 2015-02-17 |
| 8153537 | Method for fabricating semiconductor devices using stress engineering | Sai-Hooi Yeong, Tao Wang, Shesh Mani Pandey, Chia Ching Yeo, Elgin Quek | 2012-04-10 |
| 8143680 | Gated diode with non-planar source region | Da-Wen Lin, Ying-Shiou Lin, Shyh-Wei Wang, Li-Ping Huang, Carlos H. Diaz | 2012-03-27 |
| 7732877 | Gated diode with non-planar source region | Da-Wen Lin, Ying-Shiou Lin, Shyh-Wei Wang, Li-Ping Huang, Carlos H. Diaz | 2010-06-08 |
| 7012014 | Recessed gate structure with reduced current leakage and overlap capacitance | Da-Wen Lin, Yi-Ming Sheu | 2006-03-14 |
| 6747314 | Method to form a self-aligned CMOS inverter using vertical device integration | Ravi Sundaresan, Yang Pan, James Yong Meng Lee, Yelehanka Ramachandramurthy, Jia Zhen Zheng +2 more | 2004-06-08 |