Issued Patents All Time
Showing 26–49 of 49 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6661043 | One-transistor RAM approach for high density memory application | Kuo-Ching Huang, Wen-Cheng Chen, Kuo-Chuang Tseng | 2003-12-09 |
| 6638813 | Method of forming a composite spacer to eliminate polysilicon stringers between elements in a pseudo SRAM cell | Kuo-Chyuan Tzeng, Chen-Jong Wang, Chung-Wei Chang, Wen-Cheng Chen, Kuo-Ching Huang | 2003-10-28 |
| 6420226 | Method of defining a buried stack capacitor structure for a one transistor RAM cell | Wen-Cheng Chen, Kuo-Ching Huang, Chen-Jong Wang | 2002-07-16 |
| 6403416 | Method for making a double-cylinder-capacitor structure for dynamic random access memory (DRAM) | Kuo-Ching Huang, Yu-Hua Lee, James Wu | 2002-06-11 |
| 6376294 | Method to define poly dog-bone for word line strapping contact at stitch area in embedded DRAM process | Kuo-Chyuan Tzeng, Wen-Cheng Chen, Chen-Jong Wang | 2002-04-23 |
| 6306767 | Self-aligned etching method for forming high areal density patterned microelectronic structures | Kuo-Chyuan Tzeng, Tse-Liang Ying, Ming-Hsiang Chiang | 2001-10-23 |
| 6287939 | Method for fabricating a shallow trench isolation which is not susceptible to buried contact trench formation | Kuo-Ching Huang, Tse-Liang Ying | 2001-09-11 |
| 6271125 | Method to reduce contact hole aspect ratio for embedded DRAM arrays and logic devices, via the use of a tungsten bit line structure | Chue-San Yoo, Chen-Jong Wang | 2001-08-07 |
| 6235580 | Process for forming a crown shaped capacitor structure for a DRAM device | Yu-Hua Lee, Cheng-Ming Wu | 2001-05-22 |
| 6227211 | Uniformity improvement of high aspect ratio contact by stop layer | Bao Ru Yang, James J. Wu | 2001-05-08 |
| 6214715 | Method for fabricating a self aligned contact which eliminates the key hole problem using a two step spacer deposition | Kuo-Ching Huang, Tse-Liang Ying | 2001-04-10 |
| 6194234 | Method to evaluate hemisperical grain (HSG) polysilicon surface | Kuo-Ching Huang, Tse-Liang Ying, Yu-Hua Lee | 2001-02-27 |
| 6187659 | Node process integration technology to improve data retention for logic based embedded dram | Tse-Liang Ying, Cheng-Ming Wu, Yu-Hua Lee | 2001-02-13 |
| 6177340 | Method to reduce contact hole aspect ratio for embedded DRAM arrays and logic devices, via the use of a tungsten bit line structure | Chue-San Yoo, Chen-Jong Wang | 2001-01-23 |
| 6174802 | Method for fabricating a self aligned contact which eliminates the key hole problem using a two step contact deposition | Kuo-Ching Huang, Tse-Liang Ying, Min-Hsiung Chiang | 2001-01-16 |
| 6168984 | Reduction of the aspect ratio of deep contact holes for embedded DRAM devices | Chue-San Yoo, Ming-Hsiung Chiang, Cheng-Ming Wu, Tse-Liang Ying | 2001-01-02 |
| 6168989 | Process for making new and improved crown-shaped capacitors on dynamic random access memory cells | Ming-Hsiung Chiang, Cheng-Ming Wu | 2001-01-02 |
| 6165839 | Process to fabricate a cylindrical, capacitor structure under a bit line structure for a dynamic random access memory cell | Yu-Hua Lee, Cheng-Ming Wu | 2000-12-26 |
| 6143604 | Method for fabricating small-size two-step contacts for word-line strapping on dynamic random access memory (DRAM) | Ming-Hsiung Chiang, Cheng-Ming Wu | 2000-11-07 |
| 6103455 | Method to form a recess free deep contact | Kuo-Ching Huang, Cheng-Ming Wu, Yu-Hua Lee | 2000-08-15 |
| 6080637 | Shallow trench isolation technology to eliminate a kink effect | Kuo-Ching Huang, Tse-Liang Ying, Cheng-Yeh Shih | 2000-06-27 |
| 6020236 | Method to form capacitance node contacts with improved isolation in a DRAM process | Yu-Hua Lee, James Wu, Min-Hsiung Chiang | 2000-02-01 |
| 5968278 | High aspect ratio contact | Bao-Ru Young, Chia-Shiung Tsai | 1999-10-19 |
| 5922515 | Approaches to integrate the deep contact module | Tse-Liang Ying | 1999-07-13 |