Issued Patents All Time
Showing 26–34 of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6180964 | Low leakage wire bond pad structure for integrated circuits | Ho-Yin Yiu, T. Cheng | 2001-01-30 |
| 6077746 | Using p-type halo implant as ROM cell isolation in flat-cell mask ROM process | Jyh-Cheng You | 2000-06-20 |
| 5981347 | Multiple thermal annealing method for a metal oxide semiconductor field effect transistor with enhanced hot carrier effect (HCE) resistance | So-Wen Kuo, Li-Huan Chu | 1999-11-09 |
| 5953601 | ESD implantation scheme for 0.35 .mu.m 3.3V 70A gate oxide process | Ruey-Yun Shiue, Chin-Shan Hou, Yi-Hsun Wu | 1999-09-14 |
| 5942800 | Stress buffered bond pad and method of making | Ho-Yin Yiu, Bor-Cheng Chen, Jan-Her Horng | 1999-08-24 |
| 5801090 | Method of protecting an alignment mark in a semiconductor manufacturing process with CMP | Jau-Jey Wang | 1998-09-01 |
| 5747381 | Technique for the removal of residual spin-on-glass (SOG) after full SOG etchback | Chen-Hua Yu, Jin-Yuan Lee | 1998-05-05 |
| 5518959 | Method for selectively depositing silicon oxide spacer layers | Syun-Ming Jang, Chen-Hua Yu, Lung Chen | 1996-05-21 |
| 5393692 | Recessed side-wall poly plugged local oxidation | — | 1995-02-28 |