Issued Patents All Time
Showing 101–125 of 348 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12080776 | Field effect transistor with fin isolation structure and method | Yi-Ruei Jhan, Kuan-Ting Pan, Chih-Hao Wang | 2024-09-03 |
| 12074204 | Semiconductor structure and method for forming the same | Jung-Hung Chang, Lo-Heng Chang, Zhi-Chang Lin, Shih-Cheng Chen, Chien Ning Yao +1 more | 2024-08-27 |
| 12074167 | Hybrid scheme for improved performance for P-type and N-type FinFETs | Shi Ning Ju, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang | 2024-08-27 |
| 12074164 | FinFET pitch scaling | Kuan-Ting Pan, Yi-Ruei Jhan, Chih-Hao Wang | 2024-08-27 |
| 12068383 | Wrap around silicide for FinFETs | Chi-Wen Liu, Ying-Keung Leung | 2024-08-20 |
| 12068320 | Gate isolation for multigate device | Kuan-Ting Pan, Shi Ning Ju, Yi-Ruei Jhan, Kuan-Lun Cheng, Chih-Hao Wang | 2024-08-20 |
| 12062721 | Latch-up prevention | Shih-Cheng Chen, Zhi-Chang Lin | 2024-08-13 |
| 12062693 | Semiconductor device structure and methods of forming the same | Jia-Ni Yu, Mao-Lin Huang, Lung-Kun Chu, Chung-Wei Hsu, Chih-Hao Wang +1 more | 2024-08-13 |
| 12057477 | Semiconductor structure with hybrid nanostructures | Wen-Ting Lan, Guan-Lin Chen, Shi Ning Ju, Chih-Hao Wang, Ching-Wei Tsai +1 more | 2024-08-06 |
| 12057385 | Integrated circuits with backside power rails | Chih-Chao Chou, Shi Ning Ju, Wen-Ting Lan, Chih-Hao Wang | 2024-08-06 |
| 12051738 | Isolation structures of semiconductor devices | Jia-Chuan You, Chih-Hao Wang, Shi Ning Ju, Li-Yang Chuang | 2024-07-30 |
| 12051736 | Field effect transistor with inner spacer liner layer and method | Tsung-Han CHUANG, Zhi-Chang Lin, Shih-Cheng Chen, Jung-Hung Chang, Chien Ning Yao +1 more | 2024-07-30 |
| 12051693 | Method for manufacturing semiconductor structure with isolation strips | Shi Ning Ju, Kuan-Lun Cheng, Chih-Hao Wang, Kuan-Ting Pan, Zhi-Chang Lin | 2024-07-30 |
| 12040386 | Self-aligned epitaxy layer | Kuan-Lun Cheng, Chih-Hao Wang | 2024-07-16 |
| 12040371 | Multi-layer channel structures and methods of fabricating the same in field-effect transistors preliminary class | Guan-Lin Chen, Shi Ning Ju, Chih-Hao Wang, Kuan-Lun Cheng | 2024-07-16 |
| 12040329 | Semiconductor device structure and methods of forming the same | Wen-Ting Lan, Shi Ning Ju, Kuan-Lun Cheng, Chih-Hao Wang | 2024-07-16 |
| 12040191 | Semiconductor structures and methods thereof | Chung-Wei Hsu, Mao-Lin Huang, Lung-Kun Chu, Jia-Ni Yu, Kuan-Lun Cheng +1 more | 2024-07-16 |
| 12034077 | Method of forming source/drain regions with expanded widths | Chi-Wen Liu, Ying-Keung Leung | 2024-07-09 |
| 12034006 | Input/output semiconductor devices | Mao-Lin Huang, Lung-Kun Chu, Chung-Wei Hsu, Jia-Ni Yu | 2024-07-09 |
| 12034004 | Method (and related apparatus) for forming a semiconductor device with reduced spacing between nanostructure field-effect transistors | Zhi-Chang Lin, Huan-Chieh Su | 2024-07-09 |
| 12033899 | Self-aligned metal gate for multigate device | Guan-Lin Chen, Chih-Hao Wang, Ching-Wei Tsai, Shi Ning Ju, Jui-Chien Huang +1 more | 2024-07-09 |
| 12021136 | Gate isolation feature and manufacturing method thereof | Kuan-Ting Pan, Huan-Chieh Su, Jia-Chuan You, Shi Ning Ju, Yi-Ruei Jhan +2 more | 2024-06-25 |
| 12021132 | Gate patterning process for multi-gate devices | Mao-Lin Huang, Lung-Kun Chu, Chung-Wei Hsu, Jia-Ni Yu, Chih-Hao Wang | 2024-06-25 |
| 12021123 | Semiconductor devices with backside power rail and backside self-aligned via | Shi Ning Ju, Kuan-Lun Cheng, Chih-Hao Wang, Cheng-Chi Chuang | 2024-06-25 |
| 12014960 | Etch profile control of polysilicon structures of semiconductor devices | Chih-Hao Wang, Kuan-Ting Pan | 2024-06-18 |