Issued Patents All Time
Showing 76–96 of 96 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11610640 | Method for error correction coding with multiple hash groupings and device for performing the same | — | 2023-03-21 |
| 11574909 | Semiconductor device, method for manufacturing the same, and integrated circuit | Ming-Yen Chuang | 2023-02-07 |
| 11514982 | Computation unit including an asymmetric ferroelectric device pair and methods of forming the same | Chung-Te Lin | 2022-11-29 |
| 11495314 | Memory repair using optimized redundancy utilization | Chien-Hao Huang, Cheng-Yi Wu, Chung-Te Lin | 2022-11-08 |
| 11450401 | Method, system and computer program product for memory repair | Chien-Hao Huang, Cheng-Yi Wu, Chung-Te Lin | 2022-09-20 |
| 11450399 | Memory array test method and system | Chien-Hao Huang, Cheng-Yi Wu, Chung-Te Lin | 2022-09-20 |
| 11367500 | Method for LUT-free memory repair | — | 2022-06-21 |
| 11293897 | High sensitivity ISFET sensor | Jui-Cheng Huang, Ke-Wei Su, Tung-Tsun Chen, Wei-Chung Lee, Pei-Wen Liu | 2022-04-05 |
| 11282572 | Multinary bit cells for memory devices and network applications and method of manufacturing the same | Chung-Te Lin | 2022-03-22 |
| 11237907 | Processing-in-memory instruction set with homomorphic error correction | — | 2022-02-01 |
| 11145347 | Memory device and memory circuit | Hung-Li Chiang, Tzu-Chiang Chen, Ming-Yuan Song | 2021-10-12 |
| 11133044 | Interleaved routing for MRAM cell selection | Chung-Te Lin, Min Cao, Randy B. Osborne | 2021-09-28 |
| 11107859 | Memory cell with unipolar selectors | Chung-Te Lin, Mauricio Manfrini | 2021-08-31 |
| 11094361 | Transistorless memory cell | Chung-Te Lin, Min Cao, Yuh-Jier Mii, Sheng-Chih Lai | 2021-08-17 |
| 11049903 | Integrated system chip with magnetic module | Chung-Te Lin, Min Cao, Han-Ting Tsai, Pin-Cheng Hsu, Yen-Chung Ho | 2021-06-29 |
| 11030380 | Synergistic design method for fabricating integrated circuit | Chung-Te Lin | 2021-06-08 |
| 11024749 | Dual channel transistor device and methods of forming the same | Chung-Te Lin | 2021-06-01 |
| 10860769 | Method and system for integrated circuit design with on-chip variation and spatial correlation | Cheng Hsiao, Chang-Yu Huang, Juan Chen, Ke-Wei Su, Chung-Kai Lin +2 more | 2020-12-08 |
| 10839879 | Read techniques for a magnetic tunnel junction (MTJ) memory device with a current mirror | Gaurav Gupta, Chung-Te Lin | 2020-11-17 |
| 10700125 | Integrated system chip with magnetic module | Chung-Te Lin, Min Cao, Han-Ting Tsai, Pin-Cheng Hsu, Yen-Chung Ho | 2020-06-30 |
| 10521538 | Method and system for integrated circuit design with on-chip variation and spatial correlation | Cheng Hsiao, Chang-Yu Huang, Juan Chen, Ke-Wei Su, Chung-Kai Lin +2 more | 2019-12-31 |