Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12315843 | Hybrid bonding technology for stacking integrated circuits | Kuo-Ming Wu, Ching-Chun Wang, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu +3 more | 2025-05-27 |
| 11664411 | Semiconductor structure having integrated inductor therein | Ming-Che Lee, Sheng-Chau Chen, Cheng-Hsien Chou, Cheng-Yuan Tsai | 2023-05-30 |
| 11410972 | Hybrid bonding technology for stacking integrated circuits | Kuo-Ming Wu, Ching-Chun Wang, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu +3 more | 2022-08-09 |
| 11374046 | Semiconductor structure and method of manufacturing the same | Sheng-Chan Li, Tzu-Hsiang Chen, Yu-Jen Wang, Yen-Ting Chiang, Cheng-Hsien Chou +1 more | 2022-06-28 |
| 11322481 | Hybrid bonding technology for stacking integrated circuits | Kuo-Ming Wu, Ching-Chun Wang, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu +3 more | 2022-05-03 |
| 11011600 | Semiconductor structure having integrated inductor therein | Ming-Che Lee, Sheng-Chau Chen, Cheng-Hsien Chou, Cheng-Yuan Tsai | 2021-05-18 |
| 10727205 | Hybrid bonding technology for stacking integrated circuits | Kuo-Ming Wu, Ching-Chun Wang, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu +3 more | 2020-07-28 |
| 10658409 | Semiconductor structure and method of manufacturing the same | Sheng-Chan Li, Tzu-Hsiang Chen, Yu-Jen Wang, Yen-Ting Chiang, Cheng-Hsien Chou +1 more | 2020-05-19 |
| 10541297 | Semiconductor structure having integrated inductor therein | Ming-Che Lee, Sheng-Chau Chen, Cheng-Hsien Chou, Cheng-Yuan Tsai | 2020-01-21 |
| 10164001 | Semiconductor structure having integrated inductor therein | Ming-Che Lee, Sheng-Chau Chen, Cheng-Hsien Chou, Cheng-Yuan Tsai | 2018-12-25 |
| 7525848 | Method for erasing and changing data of floating gate flash memory | Yung-Hsin Wang, Ting-Kuo Yen | 2009-04-28 |