Issued Patents All Time
Showing 76–100 of 100 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6127229 | Process of forming an EEPROM device having a split gate | Wen-Ting Chu, Di-Son Kuo, Jack Y. Yeh, Chia-Ta Hsieh, Yai-Fen Lin | 2000-10-03 |
| 6124609 | Split gate flash memory with buried source to shrink cell dimension and increase coupling ratio | Chia-Ta Hsieh, Jenn Tsao, Di-Son Kuo, Yai-Fen Lin | 2000-09-26 |
| 6121088 | Method of manufacture of undoped polysilicon as the floating-gate of a split-gate flash cell | Yai-Fen Lin, Chia-Ta Hsieh, Juang-Ke Yeh, Di-Son Kuo | 2000-09-19 |
| 6117733 | Poly tip formation and self-align source process for split-gate flash cell | Di-Son Kuo, Chia-Ta Hsieh, Yai-Fen Lin | 2000-09-12 |
| 6093608 | Source side injection programming and tip erasing P-channel split gate flash memory cell | Yai-Fen Lin, Di-Son Kuo, Chia-Ta Hsieh | 2000-07-25 |
| 6090668 | Method to fabricate sharp tip of poly in split gate flash | Yai-Fen Lin, Chia-Ta Hsieh, Jung-Ke Yeh, Chang-Song Lin, Di-Son Kuo | 2000-07-18 |
| 6067254 | Method to avoid program disturb and allow shrinking the cell size in split gate flash memory | Di-Son Kuo, Yai-Fen Lin, Chia-Ta Hsieh, Jack Y. Yeh | 2000-05-23 |
| 6046086 | Method to improve the capacity of data retention and increase the coupling ratio of source to floating gate in split-gate flash | Yai-Fen Lin, Chia-Ta Hsieh, Chuang-Ke Yeh, Di-Son Kuo | 2000-04-04 |
| 6017795 | Method of fabricating buried source to shrink cell dimension and increase coupling ratio in split-gate flash | Chia-Ta Hsieh, Jenn Tsao, Di-Son Kuo, Yai-Fen Lin | 2000-01-25 |
| 6005809 | Program and erase method for a split gate flash EEPROM | Di-Son Kuo, Yai-Fen Lin, Chia-Ta Hsieh | 1999-12-21 |
| 5976927 | Two mask method for reducing field oxide encroachment in memory arrays | Chia-Ta Hsieh, Di-Son Kuo, Yai-Fen Lin | 1999-11-02 |
| 5972753 | Method of self-align cell edge implant to reduce leakage current and improve program speed in split-gate flash | Yai-Fen Lin, Chia-Ta Hsieh, Di-Son Kuo | 1999-10-26 |
| 5970371 | Method of forming sharp beak of poly to improve erase speed in split-gate flash EEPROM | Chia-Ta Hsieh, Yai-Fen Lin, Chuang-Ke Yeh, Di-Son Kuo | 1999-10-19 |
| 5962903 | Planarized plug-diode mask ROM structure | Ling Chen | 1999-10-05 |
| 5950087 | Method to make self-aligned source etching available in split-gate flash | Chia-Ta Hsieh, Yai-Fen Lin, Jaung-Ke Yeh, Kuo-Reay Peng, Di-Son Kuo | 1999-09-07 |
| 5940706 | Process for preventing misalignment in split-gate flash memory cell | Di-Son Kuo, Yai-Fen Lin, Chia-Ta Hsieh | 1999-08-17 |
| 5879992 | Method of fabricating step poly to improve program speed in split gate flash | Chia-Ta Hsieh, Yai-Fen Lin, Chuang-Ke Yeh, Di-Son Kuo | 1999-03-09 |
| 5858840 | Method of forming sharp beak of poly by nitrogen implant to improve erase speed for split-gate flash | Chia-Ta Hsieh, Yai-Fen Lin, Di-Son Kuo | 1999-01-12 |
| 5814862 | Metallic source line and drain plug with self-aligned contacts for flash memory device | Ling Chen | 1998-09-29 |
| 5751040 | Self-aligned source/drain mask ROM memory cell using trench etched channel | Ling Chen, Chi-Shiung Lo | 1998-05-12 |
| 5734607 | Method of manufacturing self-aligned bit-line and device manufactured therby | Ling Chen | 1998-03-31 |
| 5631179 | Method of manufacturing metallic source line, self-aligned contact for flash memory devices | Ling Chen | 1997-05-20 |
| 5595927 | Method for making self-aligned source/drain mask ROM memory cell using trench etched channel | Ling Chen, Chi-Shiung Lo | 1997-01-21 |
| 5589413 | Method of manufacturing self-aligned bit-line during EPROM fabrication | Ling Chen | 1996-12-31 |
| 5441907 | Process for manufacturing a plug-diode mask ROM | Ling Chen | 1995-08-15 |