Issued Patents All Time
Showing 51–75 of 100 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6344997 | Split-gate flash cell for virtual ground architecture | Din-Son Kuo, Chia-Ta Hsieh, Yai-Fen Lin | 2002-02-05 |
| 6333228 | Method to improve the control of bird's beak profile of poly in split gate flash | Chia-Ta Hsieh, Yai-Fen Lin, Jack Y. Yeh, Wen-Ting Chu, Di-Son Kuo | 2001-12-25 |
| 6326660 | Method to improve the capacity of data retention and increase the coupling ratio of source to floating gate in split-gate flash | Yai-Fen Lin, Chia-Ta Hsieh, Chuang-Ke Yeh, Di-Son Kuo | 2001-12-04 |
| 6312989 | Structure with protruding source in split-gate flash | Chia-Ta Hsieh, Yai-Fen Lin, Chuang-Ke Yeh, Wen-Ting Chu, Di-Son Kuo | 2001-11-06 |
| 6309928 | Split-gate flash cell | Di-Son Kuo, Chuang-Ke Yeh, Chia-Ta Hsieh, Yai-Fen Lin, Wen-Ting Chu | 2001-10-30 |
| 6284596 | Method of forming split-gate flash cell for salicide and self-align contact | Di-Son Kuo, Chia-Ta Hsieh | 2001-09-04 |
| 6277686 | PIP capacitor for split-gate flash process | Chung-Ker Yeh, Di-Son Kuo, Chia-Ta Hsieh, Yai-Fen Lin | 2001-08-21 |
| 6259131 | Poly tip and self aligned source for split-gate flash cell | Di-Son Kou, Chia-Ta Hsieh, Yai-Fen Lin | 2001-07-10 |
| 6251744 | Implant method to improve characteristics of high voltage isolation and high voltage breakdown | Hung-Der Su, Chrong-Jung Lin, Jong Chen, Wen-Ting Chu, Di-Son Kuo | 2001-06-26 |
| 6249454 | Split-gate flash cell for virtual ground architecture | Di-Son Kuo, Chia-Ta Hsieh, Yai-Fen Lin | 2001-06-19 |
| 6245685 | Method for forming a square oxide structure or a square floating gate structure without rounding effect | Di-Son Kuo, Chia-Ta Hsieh | 2001-06-12 |
| 6242308 | Method of forming poly tip to improve erasing and programming speed split gate flash | Chia-Ta Hsieh, Di-Son Kuo, Yai-Fen Lin | 2001-06-05 |
| 6229176 | Split gate flash with step poly to improve program speed | Chia-Ta Hsieh, Yai-Fen Lin, Chuang-Ke Yeh, Di-Son Kuo | 2001-05-08 |
| 6228695 | Method to fabricate split-gate with self-aligned source and self-aligned floating gate to control gate | Chia-Ta Hsieh, Yai-Fen Lin, Jack Y. Yeh, Di-Son Kuo | 2001-05-08 |
| 6214662 | Forming self-align source line for memory array | Di-Son Kuo, Chia-Ta Hsieh, Yai-Fen Lin | 2001-04-10 |
| 6207503 | Method for shrinking array dimensions of split gate flash memory device using multilayer etching to define cell and source line | Chia-Ta Hsieh, Yai-Fen Lin, Di-Son Kuo | 2001-03-27 |
| 6207515 | Method of fabricating buried source to shrink chip size in memory array | Chia-Ta Hsieh, Jenn Tsao, Di-Son Kuo, Yai-Fen Lin | 2001-03-27 |
| 6204126 | Method to fabricate a new structure with multi-self-aligned for split-gate flash | Chia-Ta Hsieh, Tai-Fen Lin, Wen-Ting Chu, Chuang-Ke Yeh, Di-Son Kuo | 2001-03-20 |
| 6188103 | Method of forming sharp beak of poly by nitrogen implant to improve erase speed for split-gate flash | Chia-Ta Hsieh, Yai-Fen Lin, Di-Son Kuo | 2001-02-13 |
| 6180977 | Self-aligned edge implanted cell to reduce leakage current and improve program speed in split-gate flash | Yai-Fen Lin, Chia-Ta Hsieh, Di-Son Kuo | 2001-01-30 |
| 6174772 | Optimal process flow of fabricating nitride spacer without inter-poly oxide damage in split gate flash | Chia-Ta Hsieh, Yai-Fen Lin, Jack Y. Yeh, Di-Son Kuo | 2001-01-16 |
| 6171906 | Method of forming sharp beak of poly to improve erase speed in split gate flash | Chia-Ta Hsieh, Yai-Fen Lin, Chuang-Ke Yeh, Di-Son Kuo | 2001-01-09 |
| 6165845 | Method to fabricate poly tip in split-gate flash | Chia-Ta Hsieh, Yai-Fen Lin, Jack Y. Yeh, Di-Son Kuo | 2000-12-26 |
| 6159801 | Method to increase coupling ratio of source to floating gate in split-gate flash | Chia-Ta Hsieh, Yai-Fen Lin, Di-Son Kuo, Jack Y. Yeh | 2000-12-12 |
| 6130132 | Clean process for manufacturing of split-gate flash memory device having floating gate electrode with sharp peak | Chia-Ta Hsieh, Yai-Fen Lin, Di-Son Kuo | 2000-10-10 |