Issued Patents All Time
Showing 501–525 of 525 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6707080 | Method for making spectrally efficient photodiode structures for CMOS color imagers | Ching-Chun Wang, Chien-Hsien Tseng, Shou-Gwo Wuu | 2004-03-16 |
| 6642076 | Asymmetrical reset transistor with double-diffused source for CMOS image sensor | Shou-Gwo Wuu, Ho-Ching Chien, Chien-Hsien Tseng | 2003-11-04 |
| 6635936 | SRAM layout for relaxing mechanical stress in shallow trench isolation technology | Shou-Gwo Wuu, Jin-Yuan Lee, Jeng-Han Lee | 2003-10-21 |
| 6531752 | Stripe photodiode element with high quantum efficiency for an image sensor cell | Shou-Gwo Wuu, Chien-Hsien Tseng | 2003-03-11 |
| 6518085 | Method for making spectrally efficient photodiode structures for CMOS color imagers | Ching-Chun Wang, Chien-Hsien Tseng, Shou-Gwo Wuu | 2003-02-11 |
| 6372603 | Photodiode with tightly-controlled junction profile for CMOS image sensor with STI process | Shou-Gwo Wuu, Chien-Hsien Tseng | 2002-04-16 |
| 6350662 | Method to reduce defects in shallow trench isolations by post liner anneal | Kong-Beng Thei, Kuei-Ying Lee, Shou-Gwo Wuu | 2002-02-26 |
| 6351016 | Technology for high performance buried contact and tungsten polycide gate integration | Kuo-Ching Huang, Shou-Gwo Wuu, Jenn Ming Huang | 2002-02-26 |
| 6323054 | Lateral P-I-N photodiode element with high quantum efficiency for a CMOS image sensor | Shou-Gwo Wuu, Chien-Hsien Tseng, Ching-Chun Wang | 2001-11-27 |
| 6309905 | Stripe photodiode element with high quantum efficiency for an image sensor cell | Shou-Gwo Wuu, Chien-Hsien Tseng | 2001-10-30 |
| 6271570 | Trench-free buried contact | Kuo-Ching Huang, Yean-Kuen Fang, Mong-Song Liang, Jhon Jhy Liaw, Cheng-Ming Wu | 2001-08-07 |
| 6265295 | Method of preventing tilting over | Yi-Miaw Lin, Jhon Jhy Liaw | 2001-07-24 |
| 6232194 | Silicon nitride capped poly resistor with SAC process | Shou-Gwo Wuu | 2001-05-15 |
| 6165880 | Double spacer technology for making self-aligned contacts (SAC) on semiconductor integrated circuits | Shou-Gwo Wuu, Li-Chih Chao, Kuo-Ching Huang | 2000-12-26 |
| 6136633 | Trench-free buried contact for locos isolation | Jin-Yuan Lee, Shou-Gwo Wuu | 2000-10-24 |
| 6117722 | SRAM layout for relaxing mechanical stress in shallow trench isolation technology and method of manufacture thereof | Shou-Gwo Wuu, Jin-Yuan Lee, Jeng-Han Lee | 2000-09-12 |
| 6110822 | Method for forming a polysilicon-interconnect contact in a TFT-SRAM | Kuo-Ching Huang, Yean-Kuen Fang, Mong-Song Liang | 2000-08-29 |
| 6080647 | Process to form a trench-free buried contact | Kuo-Ching Huang, Yean-Kuen Fang, Mong-Song Liang, Jhon Jhy Liaw, Cheng-Ming Wu | 2000-06-27 |
| 6078087 | SRAM memory device with improved performance | Kuo-Ching Huang, Yean-Kuen Fang, Mong-Song Liang, Cheng-Yeh Shih | 2000-06-20 |
| 6071798 | Method for fabricating buried contacts | Shou-Gwo Wuu, Jin-Yuan Lee, Jhon Jhy Liaw | 2000-06-06 |
| 6040227 | IPO deposited with low pressure O.sub.3 -TEOS for planarization in multi-poly memory technology | Shou-Gwo Wuu, Lung Chen, Yi-Miaw Lin | 2000-03-21 |
| 5998269 | Technology for high performance buried contact and tungsten polycide gate integration | Kuo-Ching Huang, Shou-Gwo Wuu, Jenn Ming Huang | 1999-12-07 |
| 5960276 | Using an extra boron implant to improve the NMOS reverse narrow width effect in shallow trench isolation process | Jhon Jhy Liaw, Jin-Yuan Lee | 1999-09-28 |
| 5953606 | Method for manufacturing a TFT SRAM memory device with improved performance | Kuo-Ching Huang, Yean-Kuen Fang, Mong-Song Liang, Cheng-Yeh Shih | 1999-09-14 |
| 5926697 | Method of forming a moisture guard ring for integrated circuit applications | Shou-Gwo Wuu, Jin-Yuan Lee, Hsien-Wei Chin | 1999-07-20 |