Issued Patents All Time
Showing 126–150 of 152 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7494857 | Advanced activation approach for MOS devices | Tze-Liang Lee, Shih-Chang Chen, Keh-Chiang Ku, Chun-Feng Nieh, Li-Ting Wang +1 more | 2009-02-24 |
| 7482211 | Junction leakage reduction in SiGe process by implantation | Chun-Feng Nieh, Keh-Chiang Ku, Tze-Liang Lee, Shih-Chang Chen | 2009-01-27 |
| 7393766 | Process for integration of a high dielectric constant gate insulator layer in a CMOS device | Ming-Fang Wang, Liang-Gi Yao, Shih-Chang Chen | 2008-07-01 |
| 7361572 | STI liner modification method | Vincent S. Chang, Chia-Lin Chen, Tze-Liang Lee, Shih-Chang Chen | 2008-04-22 |
| 7335544 | Method of making MOSFET device with localized stressor | Donald Y. Chao, Tze-Liang Lee, Shih-Chang Chen | 2008-02-26 |
| 7327009 | Selective nitride liner formation for shallow trench isolation | Vincent S. Chang, Ji-Yi Yang, Chia-Lin Chen, Tze-Liang Lee | 2008-02-05 |
| 7316970 | Method for forming high selectivity protection layer on semiconductor device | Ju-Wang Hsu, Chia-Lin Chen, Tze-Liang Lee, Shih-Chang Chen | 2008-01-08 |
| 7259050 | Semiconductor device and method of making the same | Chia-Lin Chen, Tze-Liang Lee, Shih-Chang Chen, Ju-Wang Hsu | 2007-08-21 |
| 7232730 | Method of forming a locally strained transistor | Donald Y. Chao, Tze-Liang Lee | 2007-06-19 |
| 7223647 | Method for forming integrated advanced semiconductor device using sacrificial stress layer | Ju-Wang Hsu, Ming-Huan Tsai, Yi-Chun Huang | 2007-05-29 |
| 7186662 | Method for forming a hard mask for gate electrode patterning and corresponding device | Chia-Jen Chen, Tze-Liang Lee, Chao-Cheng Chen, Shih-Chang Chen | 2007-03-06 |
| 7176138 | Selective nitride liner formation for shallow trench isolation | Vincent S. Chang, Ji-Yi Yang, Chia-Lin Chen, Tze-Liang Lee | 2007-02-13 |
| 7166525 | High temperature hydrogen annealing of a gate insulator layer to increase etching selectivity between conductive gate structure and gate insulator layer | Vincent S. Chang, Chia-Lin Chen, Chi-Chun Chen, Tze-Liang Lee, Shih-Chang Chen | 2007-01-23 |
| 7164163 | Strained transistor with hybrid-strain inducing layer | Tze-Liang Lee | 2007-01-16 |
| 7157350 | Method of forming SOI-like structure in a bulk semiconductor substrate using self-organized atomic migration | Ji-Yi Yang, Tze-Liang Lee, Shih-Chang Chen, Huan-Just Lin | 2007-01-02 |
| 7149034 | Assessing mark for microlens | En-Ting Liu, Hsin-Wei Lin, Der-Yu Chou | 2006-12-12 |
| 7138317 | Method of generating multiple oxides by plasma nitridation on oxide | Chia-Lin Chen, Mo Yu | 2006-11-21 |
| 7118974 | Method of generating multiple oxides by plasma nitridation on oxide | Chia-Lin Chen, Mo Yu | 2006-10-10 |
| 7087508 | Method of improving short channel effect and gate oxide reliability by nitrogen plasma treatment before spacer deposition | Juing-Yi Cheng | 2006-08-08 |
| 7052946 | Method for selectively stressing MOSFETs to improve charge carrier mobility | Chia-Lin Chen, Ju-Wang Hsu, Tze-Liang Lee, Shih-Chang Chen | 2006-05-30 |
| 7018879 | Method of making an ultrathin silicon dioxide gate with improved dielectric properties using NH3 nitridation and post-deposition rapid thermal annealing | Ming-Fang Wang, Liang-Gi Yao, Shih-Chang Chen | 2006-03-28 |
| 6914313 | Process for integration of a high dielectric constant gate insulator layer in a CMOS device | Ming-Fang Wang, Liang-Gi Yao, Shih-Chang Chen | 2005-07-05 |
| 6767847 | Method of forming a silicon nitride-silicon dioxide gate stack | Chien-Ming Hu, Mo Yu, Shih-Chang Chen, Mong-Song Liang | 2004-07-27 |
| 6759302 | Method of generating multiple oxides by plasma nitridation on oxide | Chia-Lin Chen, Mo Yu | 2004-07-06 |
| 6656764 | Process for integration of a high dielectric constant gate insulator layer in a CMOS device | Ming-Fang Wang, Liang-Gi Yao, Shih-Chang Chen | 2003-12-02 |