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Measuring device defect sensitization in transistor-level circuits |
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Finding equivalent classes of hard defects in stacked MOSFET arrays |
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| 11797737 |
Finding equivalent classes of hard defects in stacked MOSFET arrays |
Michal Jerzy Rewienski, Shan-Fu Yuan, Michael Joseph Durr, Chih Ping Antony Fan |
2023-10-24 |
| 11763056 |
Method and system for custom model definition of analog defects in an integrated circuit |
Michael Joseph Durr, Mira Tzakova, Beatrice Solignac, Rayson Yam |
2023-09-19 |
| 11734482 |
Visual representation to assess quality of input stimulus in transistor-level circuits |
Aleksandrs Krjukovs, Chih Ping Antony Fan |
2023-08-22 |
| 11669667 |
Automatic test pattern generation (ATPG) for parametric faults |
Peilin Jiang, Chih Ping Antony Fan |
2023-06-06 |
| 11620424 |
Transistor—level defect coverage and defect simulation |
Sayandeep Sanyal, Amit Patra, Pallab Dasgupta |
2023-04-04 |
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Fast and scalable methodology for analog defect detectability analysis |
Huiping Huang, Antony Fan |
2023-02-14 |
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Defect weight formulas for analog defect simulation |
Miroslava Tzakova, Chih Ping Antony Fan |
2022-09-13 |
| 11361135 |
Guiding sample size choice in analog defect or fault simulation |
Mihir Sherlekar, Antony Fan |
2022-06-14 |
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Multi-piece jaw assembly for surgical clip applier |
Anil K. Nalagatla, Frederick E. Shelton, IV, Chester O. Baxter, III, Amit Gupta |
2021-10-12 |
| 10409941 |
Visual representation of circuit related data |
Chih Ping Antony Fan, Huiping Huang, Vinay Nulkar, Amelia Huimin Shen |
2019-09-10 |
| 9032352 |
Method of optimizing capacitive couplings in high-capacitance nets in simulation of post-layout circuits |
Michal Jerzy Rewienski, Amelia Huimin Shen |
2015-05-12 |
| 8060355 |
Automatic, hierarchy-independent partitioning method for transistor-level circuit simulation |
Kevin J. Kerns, Svetlana Rudnaya, Kiran Kumar Gullapalli |
2011-11-15 |
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High-speed, compact, edge-triggered, flip-flop circuit |
Shriram Kulkarni, Pinaki Mazumder |
2001-11-27 |
