Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8091052 | Optimization of post-layout arrays of cells for accelerated transistor level simulation | Michal Jerzy Rewienski | 2012-01-03 |
| 8060355 | Automatic, hierarchy-independent partitioning method for transistor-level circuit simulation | Mayukh Bhattacharya, Svetlana Rudnaya, Kiran Kumar Gullapalli | 2011-11-15 |
| 7324363 | SPICE optimized for arrays | Zhishi Peng | 2008-01-29 |