Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10229234 | Method and apparatus to facilitate simulating a circuit connected to a multiport interconnect structure | — | 2019-03-12 |
| 9449129 | Method and apparatus for accelerating sparse matrix operations in full accuracy circuit simulation | Steven D. Hamm | 2016-09-20 |
| 9135383 | Table model circuit simulation acceleration using model caching | Steven D. Hamm | 2015-09-15 |
| 8886508 | Circuit simulation acceleration using model caching | Steven D. Hamm | 2014-11-11 |
| 8060355 | Automatic, hierarchy-independent partitioning method for transistor-level circuit simulation | Kevin J. Kerns, Mayukh Bhattacharya, Svetlana Rudnaya | 2011-11-15 |
| 7007253 | Method and apparatus for distortion analysis in nonlinear circuits | Mark M. Gourary, Sergei G. Rusakov, Sergei L. Ulyanov, Mikhail M. Zharov | 2006-02-28 |
| 6536026 | Method and apparatus for analyzing small signal response and noise in nonlinear circuits | — | 2003-03-18 |
| 5799172 | Method of simulating an integrated circuit | Brian J. Mulvaney, Steven D. Hamm, Steven R. Beckerich | 1998-08-25 |
| 5687355 | Apparatus and method for modeling a graded channel transistor | Kuntal Joardar | 1997-11-11 |
| 5408107 | Semiconductor device apparatus having multiple current-voltage curves and zero-bias memory | Dean P. Neikirk | 1995-04-18 |