MR

Michal Jerzy Rewienski

SY Synopsys: 4 patents #328 of 2,302Top 15%
Overall (All Time): #1,078,905 of 4,157,543Top 30%
4
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12271668 Finding equivalent classes of hard defects in stacked MOSFET arrays Mayukh Bhattacharya, Shan-Fu Yuan, Michael Joseph Durr, Chih Ping Antony Fan 2025-04-08
11797737 Finding equivalent classes of hard defects in stacked MOSFET arrays Mayukh Bhattacharya, Shan-Fu Yuan, Michael Joseph Durr, Chih Ping Antony Fan 2023-10-24
9032352 Method of optimizing capacitive couplings in high-capacitance nets in simulation of post-layout circuits Mayukh Bhattacharya, Amelia Huimin Shen 2015-05-12
8091052 Optimization of post-layout arrays of cells for accelerated transistor level simulation Kevin J. Kerns 2012-01-03